2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include "arch/mips/faults.hh"
35 #include "arch/mips/pra_constants.hh"
36 #include "base/trace.hh"
37 #include "cpu/base.hh"
38 #include "cpu/thread_context.hh"
39 #include "debug/MipsPRA.hh"
42 #include "mem/page_table.hh"
43 #include "sim/process.hh"
49 typedef MipsFaultBase::FaultVals FaultVals
;
51 template <> FaultVals MipsFault
<SystemCallFault
>::vals
=
52 { "Syscall", 0x180, ExcCodeSys
};
54 template <> FaultVals MipsFault
<ReservedInstructionFault
>::vals
=
55 { "Reserved Instruction Fault", 0x180, ExcCodeRI
};
57 template <> FaultVals MipsFault
<ThreadFault
>::vals
=
58 { "Thread Fault", 0x180, ExcCodeDummy
};
60 template <> FaultVals MipsFault
<IntegerOverflowFault
>::vals
=
61 { "Integer Overflow Exception", 0x180, ExcCodeOv
};
63 template <> FaultVals MipsFault
<TrapFault
>::vals
=
64 { "Trap", 0x180, ExcCodeTr
};
66 template <> FaultVals MipsFault
<BreakpointFault
>::vals
=
67 { "Breakpoint", 0x180, ExcCodeBp
};
69 template <> FaultVals MipsFault
<DspStateDisabledFault
>::vals
=
70 { "DSP Disabled Fault", 0x180, ExcCodeDummy
};
72 template <> FaultVals MipsFault
<MachineCheckFault
>::vals
=
73 { "Machine Check", 0x180, ExcCodeMCheck
};
75 template <> FaultVals MipsFault
<ResetFault
>::vals
=
76 { "Reset Fault", 0x000, ExcCodeDummy
};
78 template <> FaultVals MipsFault
<SoftResetFault
>::vals
=
79 { "Soft Reset Fault", 0x000, ExcCodeDummy
};
81 template <> FaultVals MipsFault
<NonMaskableInterrupt
>::vals
=
82 { "Non Maskable Interrupt", 0x000, ExcCodeDummy
};
84 template <> FaultVals MipsFault
<CoprocessorUnusableFault
>::vals
=
85 { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU
};
87 template <> FaultVals MipsFault
<InterruptFault
>::vals
=
88 { "Interrupt", 0x000, ExcCodeInt
};
90 template <> FaultVals MipsFault
<AddressErrorFault
>::vals
=
91 { "Address Error", 0x180, ExcCodeDummy
};
93 template <> FaultVals MipsFault
<TlbInvalidFault
>::vals
=
94 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy
};
96 template <> FaultVals MipsFault
<TlbRefillFault
>::vals
=
97 { "TLB Refill Exception", 0x180, ExcCodeDummy
};
99 template <> FaultVals MipsFault
<TlbModifiedFault
>::vals
=
100 { "TLB Modified Exception", 0x180, ExcCodeMod
};
103 MipsFaultBase::setExceptionState(ThreadContext
*tc
, uint8_t excCode
)
105 // modify SRS Ctl - Save CSS, put ESS into CSS
106 StatusReg status
= tc
->readMiscReg(MISCREG_STATUS
);
107 if (status
.exl
!= 1 && status
.bev
!= 1) {
108 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
109 SRSCtlReg srsCtl
= tc
->readMiscReg(MISCREG_SRSCTL
);
110 srsCtl
.pss
= srsCtl
.css
;
111 srsCtl
.css
= srsCtl
.ess
;
112 tc
->setMiscRegNoEffect(MISCREG_SRSCTL
, srsCtl
);
115 // set EXL bit (don't care if it is already set!)
117 tc
->setMiscRegNoEffect(MISCREG_STATUS
, status
);
120 PCState pc
= tc
->pcState();
121 DPRINTF(MipsPRA
, "PC: %s\n", pc
);
122 bool delay_slot
= pc
.pc() + sizeof(MachInst
) != pc
.npc();
123 tc
->setMiscRegNoEffect(MISCREG_EPC
,
124 pc
.pc() - delay_slot
? sizeof(MachInst
) : 0);
126 // Set Cause_EXCCODE field
127 CauseReg cause
= tc
->readMiscReg(MISCREG_CAUSE
);
128 cause
.excCode
= excCode
;
129 cause
.bd
= delay_slot
? 1 : 0;
131 tc
->setMiscRegNoEffect(MISCREG_CAUSE
, cause
);
135 MipsFaultBase::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
138 DPRINTF(MipsPRA
, "Fault %s encountered.\n", name());
139 setExceptionState(tc
, code());
140 tc
->pcState(vect(tc
));
142 panic("Fault %s encountered.\n", name());
147 ResetFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
150 DPRINTF(MipsPRA
, "%s encountered.\n", name());
151 /* All reset activity must be invoked from here */
152 Addr handler
= vect(tc
);
153 tc
->pcState(handler
);
154 DPRINTF(MipsPRA
, "ResetFault::invoke : PC set to %x", handler
);
157 // Set Coprocessor 1 (Floating Point) To Usable
158 StatusReg status
= tc
->readMiscRegNoEffect(MISCREG_STATUS
);
160 tc
->setMiscReg(MISCREG_STATUS
, status
);
164 SoftResetFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
166 panic("Soft reset not implemented.\n");
170 NonMaskableInterrupt::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
172 panic("Non maskable interrupt not implemented.\n");
175 } // namespace MipsISA