2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
31 #include "arch/mips/faults.hh"
32 #include "cpu/thread_context.hh"
33 #include "cpu/base.hh"
34 #include "base/trace.hh"
39 FaultName
MachineCheckFault::_name
= "Machine Check";
40 FaultVect
MachineCheckFault::_vect
= 0x0401;
41 FaultStat
MachineCheckFault::_count
;
43 FaultName
AlignmentFault::_name
= "Alignment";
44 FaultVect
AlignmentFault::_vect
= 0x0301;
45 FaultStat
AlignmentFault::_count
;
47 FaultName
ResetFault::_name
= "reset";
48 FaultVect
ResetFault::_vect
= 0x0001;
49 FaultStat
ResetFault::_count
;
51 FaultName
ArithmeticFault::_name
= "arith";
52 FaultVect
ArithmeticFault::_vect
= 0x0501;
53 FaultStat
ArithmeticFault::_count
;
55 FaultName
InterruptFault::_name
= "interrupt";
56 FaultVect
InterruptFault::_vect
= 0x0101;
57 FaultStat
InterruptFault::_count
;
59 FaultName
NDtbMissFault::_name
= "dtb_miss_single";
60 FaultVect
NDtbMissFault::_vect
= 0x0201;
61 FaultStat
NDtbMissFault::_count
;
63 FaultName
PDtbMissFault::_name
= "dtb_miss_double";
64 FaultVect
PDtbMissFault::_vect
= 0x0281;
65 FaultStat
PDtbMissFault::_count
;
67 FaultName
DtbPageFault::_name
= "dfault";
68 FaultVect
DtbPageFault::_vect
= 0x0381;
69 FaultStat
DtbPageFault::_count
;
71 FaultName
DtbAcvFault::_name
= "dfault";
72 FaultVect
DtbAcvFault::_vect
= 0x0381;
73 FaultStat
DtbAcvFault::_count
;
75 FaultName
ItbMissFault::_name
= "itbmiss";
76 FaultVect
ItbMissFault::_vect
= 0x0181;
77 FaultStat
ItbMissFault::_count
;
79 FaultName
ItbPageFault::_name
= "itbmiss";
80 FaultVect
ItbPageFault::_vect
= 0x0181;
81 FaultStat
ItbPageFault::_count
;
83 FaultName
ItbAcvFault::_name
= "iaccvio";
84 FaultVect
ItbAcvFault::_vect
= 0x0081;
85 FaultStat
ItbAcvFault::_count
;
87 FaultName
UnimplementedOpcodeFault::_name
= "opdec";
88 FaultVect
UnimplementedOpcodeFault::_vect
= 0x0481;
89 FaultStat
UnimplementedOpcodeFault::_count
;
91 FaultName
FloatEnableFault::_name
= "fen";
92 FaultVect
FloatEnableFault::_vect
= 0x0581;
93 FaultStat
FloatEnableFault::_count
;
95 FaultName
PalFault::_name
= "pal";
96 FaultVect
PalFault::_vect
= 0x2001;
97 FaultStat
PalFault::_count
;
99 FaultName
IntegerOverflowFault::_name
= "intover";
100 FaultVect
IntegerOverflowFault::_vect
= 0x0501;
101 FaultStat
IntegerOverflowFault::_count
;
105 void MipsFault::invoke(ThreadContext
* tc
)
107 FaultBase::invoke(tc
);
110 // exception restart address
111 if (setRestartAddress() || !tc
->inPalMode())
112 tc
->setMiscReg(MipsISA::IPR_EXC_ADDR
, tc
->readPC());
114 if (skipFaultingInstruction()) {
115 // traps... skip faulting instruction.
116 tc
->setMiscReg(MipsISA::IPR_EXC_ADDR
,
117 tc
->readMiscReg(MipsISA::IPR_EXC_ADDR
) + 4);
120 tc
->setPC(tc
->readMiscReg(MipsISA::IPR_PAL_BASE
) + vect());
121 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
124 void ArithmeticFault::invoke(ThreadContext
* tc
)
126 FaultBase::invoke(tc
);
127 panic("Arithmetic traps are unimplemented!");
132 } // namespace MipsISA