2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
6 * Redistribution and use in source and binary forms, with or without
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10 * redistributions in binary form must reproduce the above copyright
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13 * neither the name of the copyright holders nor the names of its
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15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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34 #include "arch/mips/faults.hh"
35 #include "arch/mips/pra_constants.hh"
36 #include "base/trace.hh"
37 #include "cpu/base.hh"
38 #include "cpu/thread_context.hh"
39 #include "debug/MipsPRA.hh"
40 #include "mem/page_table.hh"
41 #include "sim/process.hh"
46 typedef MipsFaultBase::FaultVals FaultVals
;
48 template <> FaultVals MipsFault
<SystemCallFault
>::vals
=
49 { "Syscall", 0x180, ExcCodeSys
};
51 template <> FaultVals MipsFault
<ReservedInstructionFault
>::vals
=
52 { "Reserved Instruction Fault", 0x180, ExcCodeRI
};
54 template <> FaultVals MipsFault
<ThreadFault
>::vals
=
55 { "Thread Fault", 0x180, ExcCodeDummy
};
57 template <> FaultVals MipsFault
<IntegerOverflowFault
>::vals
=
58 { "Integer Overflow Exception", 0x180, ExcCodeOv
};
60 template <> FaultVals MipsFault
<TrapFault
>::vals
=
61 { "Trap", 0x180, ExcCodeTr
};
63 template <> FaultVals MipsFault
<BreakpointFault
>::vals
=
64 { "Breakpoint", 0x180, ExcCodeBp
};
66 template <> FaultVals MipsFault
<DspStateDisabledFault
>::vals
=
67 { "DSP Disabled Fault", 0x180, ExcCodeDummy
};
69 template <> FaultVals MipsFault
<MachineCheckFault
>::vals
=
70 { "Machine Check", 0x180, ExcCodeMCheck
};
72 template <> FaultVals MipsFault
<ResetFault
>::vals
=
73 { "Reset Fault", 0x000, ExcCodeDummy
};
75 template <> FaultVals MipsFault
<SoftResetFault
>::vals
=
76 { "Soft Reset Fault", 0x000, ExcCodeDummy
};
78 template <> FaultVals MipsFault
<NonMaskableInterrupt
>::vals
=
79 { "Non Maskable Interrupt", 0x000, ExcCodeDummy
};
81 template <> FaultVals MipsFault
<CoprocessorUnusableFault
>::vals
=
82 { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU
};
84 template <> FaultVals MipsFault
<InterruptFault
>::vals
=
85 { "Interrupt", 0x000, ExcCodeInt
};
87 template <> FaultVals MipsFault
<AddressErrorFault
>::vals
=
88 { "Address Error", 0x180, ExcCodeDummy
};
90 template <> FaultVals MipsFault
<TlbInvalidFault
>::vals
=
91 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy
};
93 template <> FaultVals MipsFault
<TlbRefillFault
>::vals
=
94 { "TLB Refill Exception", 0x180, ExcCodeDummy
};
96 template <> FaultVals MipsFault
<TlbModifiedFault
>::vals
=
97 { "TLB Modified Exception", 0x180, ExcCodeMod
};
100 MipsFaultBase::setExceptionState(ThreadContext
*tc
, uint8_t excCode
)
102 // modify SRS Ctl - Save CSS, put ESS into CSS
103 StatusReg status
= tc
->readMiscReg(MISCREG_STATUS
);
104 if (status
.exl
!= 1 && status
.bev
!= 1) {
105 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
106 SRSCtlReg srsCtl
= tc
->readMiscReg(MISCREG_SRSCTL
);
107 srsCtl
.pss
= srsCtl
.css
;
108 srsCtl
.css
= srsCtl
.ess
;
109 tc
->setMiscRegNoEffect(MISCREG_SRSCTL
, srsCtl
);
112 // set EXL bit (don't care if it is already set!)
114 tc
->setMiscRegNoEffect(MISCREG_STATUS
, status
);
117 PCState pc
= tc
->pcState();
118 DPRINTF(MipsPRA
, "PC: %s\n", pc
);
119 bool delay_slot
= pc
.pc() + sizeof(MachInst
) != pc
.npc();
120 tc
->setMiscRegNoEffect(MISCREG_EPC
,
121 pc
.pc() - delay_slot
? sizeof(MachInst
) : 0);
123 // Set Cause_EXCCODE field
124 CauseReg cause
= tc
->readMiscReg(MISCREG_CAUSE
);
125 cause
.excCode
= excCode
;
126 cause
.bd
= delay_slot
? 1 : 0;
128 tc
->setMiscRegNoEffect(MISCREG_CAUSE
, cause
);
132 MipsFaultBase::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
135 DPRINTF(MipsPRA
, "Fault %s encountered.\n", name());
136 setExceptionState(tc
, code());
137 tc
->pcState(vect(tc
));
139 panic("Fault %s encountered.\n", name());
144 ResetFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
147 DPRINTF(MipsPRA
, "%s encountered.\n", name());
148 /* All reset activity must be invoked from here */
149 Addr handler
= vect(tc
);
150 tc
->pcState(handler
);
151 DPRINTF(MipsPRA
, "ResetFault::invoke : PC set to %x", handler
);
154 // Set Coprocessor 1 (Floating Point) To Usable
155 StatusReg status
= tc
->readMiscRegNoEffect(MISCREG_STATUS
);
157 tc
->setMiscReg(MISCREG_STATUS
, status
);
161 SoftResetFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
163 panic("Soft reset not implemented.\n");
167 NonMaskableInterrupt::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
169 panic("Non maskable interrupt not implemented.\n");
172 } // namespace MipsISA