2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
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10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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36 #include "arch/mips/faults.hh"
37 #include "arch/mips/pra_constants.hh"
38 #include "base/trace.hh"
39 #include "cpu/base.hh"
40 #include "cpu/thread_context.hh"
41 #include "debug/MipsPRA.hh"
44 #include "mem/page_table.hh"
45 #include "sim/process.hh"
51 typedef MipsFaultBase::FaultVals FaultVals
;
53 template <> FaultVals MipsFault
<SystemCallFault
>::vals
=
54 { "Syscall", 0x180, ExcCodeSys
};
56 template <> FaultVals MipsFault
<ReservedInstructionFault
>::vals
=
57 { "Reserved Instruction Fault", 0x180, ExcCodeRI
};
59 template <> FaultVals MipsFault
<ThreadFault
>::vals
=
60 { "Thread Fault", 0x180, ExcCodeDummy
};
62 template <> FaultVals MipsFault
<IntegerOverflowFault
>::vals
=
63 { "Integer Overflow Exception", 0x180, ExcCodeOv
};
65 template <> FaultVals MipsFault
<TrapFault
>::vals
=
66 { "Trap", 0x180, ExcCodeTr
};
68 template <> FaultVals MipsFault
<BreakpointFault
>::vals
=
69 { "Breakpoint", 0x180, ExcCodeBp
};
71 template <> FaultVals MipsFault
<DspStateDisabledFault
>::vals
=
72 { "DSP Disabled Fault", 0x180, ExcCodeDummy
};
74 template <> FaultVals MipsFault
<MachineCheckFault
>::vals
=
75 { "Machine Check", 0x180, ExcCodeMCheck
};
77 template <> FaultVals MipsFault
<ResetFault
>::vals
=
78 { "Reset Fault", 0x000, ExcCodeDummy
};
80 template <> FaultVals MipsFault
<SoftResetFault
>::vals
=
81 { "Soft Reset Fault", 0x000, ExcCodeDummy
};
83 template <> FaultVals MipsFault
<NonMaskableInterrupt
>::vals
=
84 { "Non Maskable Interrupt", 0x000, ExcCodeDummy
};
86 template <> FaultVals MipsFault
<CoprocessorUnusableFault
>::vals
=
87 { "Coprocessor Unusable Fault", 0x180, ExcCodeCpU
};
89 template <> FaultVals MipsFault
<InterruptFault
>::vals
=
90 { "Interrupt", 0x000, ExcCodeInt
};
92 template <> FaultVals MipsFault
<AddressErrorFault
>::vals
=
93 { "Address Error", 0x180, ExcCodeDummy
};
95 template <> FaultVals MipsFault
<TlbInvalidFault
>::vals
=
96 { "Invalid TLB Entry Exception", 0x180, ExcCodeDummy
};
98 template <> FaultVals MipsFault
<TlbRefillFault
>::vals
=
99 { "TLB Refill Exception", 0x180, ExcCodeDummy
};
101 template <> FaultVals MipsFault
<TlbModifiedFault
>::vals
=
102 { "TLB Modified Exception", 0x180, ExcCodeMod
};
105 MipsFaultBase::setExceptionState(ThreadContext
*tc
, uint8_t excCode
)
107 // modify SRS Ctl - Save CSS, put ESS into CSS
108 StatusReg status
= tc
->readMiscReg(MISCREG_STATUS
);
109 if (status
.exl
!= 1 && status
.bev
!= 1) {
110 // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
111 SRSCtlReg srsCtl
= tc
->readMiscReg(MISCREG_SRSCTL
);
112 srsCtl
.pss
= srsCtl
.css
;
113 srsCtl
.css
= srsCtl
.ess
;
114 tc
->setMiscRegNoEffect(MISCREG_SRSCTL
, srsCtl
);
117 // set EXL bit (don't care if it is already set!)
119 tc
->setMiscRegNoEffect(MISCREG_STATUS
, status
);
122 PCState pc
= tc
->pcState();
123 DPRINTF(MipsPRA
, "PC: %s\n", pc
);
124 bool delay_slot
= pc
.pc() + sizeof(MachInst
) != pc
.npc();
125 tc
->setMiscRegNoEffect(MISCREG_EPC
,
126 pc
.pc() - (delay_slot
? sizeof(MachInst
) : 0));
128 // Set Cause_EXCCODE field
129 CauseReg cause
= tc
->readMiscReg(MISCREG_CAUSE
);
130 cause
.excCode
= excCode
;
131 cause
.bd
= delay_slot
? 1 : 0;
133 tc
->setMiscRegNoEffect(MISCREG_CAUSE
, cause
);
137 MipsFaultBase::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
140 DPRINTF(MipsPRA
, "Fault %s encountered.\n", name());
141 setExceptionState(tc
, code());
142 tc
->pcState(vect(tc
));
144 panic("Fault %s encountered.\n", name());
149 ResetFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
152 DPRINTF(MipsPRA
, "%s encountered.\n", name());
153 /* All reset activity must be invoked from here */
154 Addr handler
= vect(tc
);
155 tc
->pcState(handler
);
156 DPRINTF(MipsPRA
, "ResetFault::invoke : PC set to %x", handler
);
159 // Set Coprocessor 1 (Floating Point) To Usable
160 StatusReg status
= tc
->readMiscRegNoEffect(MISCREG_STATUS
);
162 tc
->setMiscReg(MISCREG_STATUS
, status
);
166 SoftResetFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
168 panic("Soft reset not implemented.\n");
172 NonMaskableInterrupt::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
174 panic("Non maskable interrupt not implemented.\n");
177 } // namespace MipsISA