src/arch/mips/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Gabe Black
  30  *          Korey Sewell
  31  *          Jaidev Patwardhan
  32  */
  33
  34 #include "arch/mips/faults.hh"
  35 #include "arch/mips/pra_constants.hh"
  36 #include "base/trace.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/thread_context.hh"
  39 #include "debug/MipsPRA.hh"
  40
  41 #if !FULL_SYSTEM
  42 #include "mem/page_table.hh"
  43 #include "sim/process.hh"
  44 #endif
  45
  46 namespace MipsISA
  47 {
  48
  49 typedef MipsFaultBase::FaultVals FaultVals;
  50
  51 template <> FaultVals MipsFault<MachineCheckFault>::vals =
  52     { "Machine Check", 0x0401 };
  53
  54 template <> FaultVals MipsFault<ResetFault>::vals =
  55 #if  FULL_SYSTEM
  56     { "Reset Fault", 0xBFC00000};
  57 #else
  58     { "Reset Fault", 0x001};
  59 #endif
  60
  61 template <> FaultVals MipsFault<AddressErrorFault>::vals =
  62     { "Address Error", 0x0180 };
  63
  64 template <> FaultVals MipsFault<SystemCallFault>::vals =
  65     { "Syscall", 0x0180 };
  66
  67 template <> FaultVals MipsFault<CoprocessorUnusableFault>::vals =
  68     { "Coprocessor Unusable Fault", 0x180 };
  69
  70 template <> FaultVals MipsFault<ReservedInstructionFault>::vals =
  71     { "Reserved Instruction Fault", 0x0180 };
  72
  73 template <> FaultVals MipsFault<ThreadFault>::vals =
  74     { "Thread Fault", 0x00F1 };
  75
  76 template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
  77     { "Integer Overflow Exception", 0x180 };
  78
  79 template <> FaultVals MipsFault<InterruptFault>::vals =
  80     { "interrupt", 0x0180 };
  81
  82 template <> FaultVals MipsFault<TrapFault>::vals =
  83     { "Trap", 0x0180 };
  84
  85 template <> FaultVals MipsFault<BreakpointFault>::vals =
  86     { "Breakpoint", 0x0180 };
  87
  88 template <> FaultVals MipsFault<TlbInvalidFault>::vals =
  89     { "Invalid TLB Entry Exception", 0x0180 };
  90
  91 template <> FaultVals MipsFault<TlbRefillFault>::vals =
  92     { "TLB Refill Exception", 0x0180 };
  93
  94 template <> FaultVals MipsFault<TlbModifiedFault>::vals =
  95     { "TLB Modified Exception", 0x0180 };
  96
  97 template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
  98     { "DSP Disabled Fault", 0x001a };
  99
 100 void
 101 MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
 102 {
 103     // modify SRS Ctl - Save CSS, put ESS into CSS
 104     StatusReg status = tc->readMiscReg(MISCREG_STATUS);
 105     if (status.exl != 1 && status.bev != 1) {
 106         // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
 107         SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
 108         srsCtl.pss = srsCtl.css;
 109         srsCtl.css = srsCtl.ess;
 110         tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
 111     }
 112
 113     // set EXL bit (don't care if it is already set!)
 114     status.exl = 1;
 115     tc->setMiscRegNoEffect(MISCREG_STATUS, status);
 116
 117     // write EPC
 118     PCState pc = tc->pcState();
 119     DPRINTF(MipsPRA, "PC: %s\n", pc);
 120     bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
 121     tc->setMiscRegNoEffect(MISCREG_EPC,
 122             pc.pc() - delay_slot ? sizeof(MachInst) : 0);
 123
 124     // Set Cause_EXCCODE field
 125     CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
 126     cause.excCode = excCode;
 127     cause.bd = delay_slot ? 1 : 0;
 128     cause.ce = 0;
 129     tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
 130 }
 131
 132 #if FULL_SYSTEM
 133
 134 void
 135 IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 136 {
 137     DPRINTF(MipsPRA, "%s encountered.\n", name());
 138     setExceptionState(tc, 0xC);
 139
 140     // Set new PC
 141     StatusReg status = tc->readMiscReg(MISCREG_STATUS);
 142     if (!status.bev) {
 143         // See MIPS ARM Vol 3, Revision 2, Page 38
 144         tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
 145     } else {
 146         tc->pcState(0xBFC00200);
 147     }
 148 }
 149
 150 void
 151 TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 152 {
 153     DPRINTF(MipsPRA, "%s encountered.\n", name());
 154     setExceptionState(tc, 0xD);
 155
 156     tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
 157 }
 158
 159 void
 160 BreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 161 {
 162     setExceptionState(tc, 0x9);
 163
 164     tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
 165 }
 166
 167 void
 168 AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 169 {
 170     DPRINTF(MipsPRA, "%s encountered.\n", name());
 171     setExceptionState(tc, store ? 0x5 : 0x4);
 172     tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
 173
 174     tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
 175 }
 176
 177 void
 178 TlbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 179 {
 180     setTlbExceptionState(tc, store ? 0x3 : 0x2);
 181     tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
 182 }
 183
 184 void
 185 TlbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 186 {
 187     // Since handler depends on EXL bit, must check EXL bit before setting it!!
 188     StatusReg status = tc->readMiscReg(MISCREG_STATUS);
 189
 190     setTlbExceptionState(tc, store ? 0x3 : 0x2);
 191
 192     // See MIPS ARM Vol 3, Revision 2, Page 38
 193     if (status.exl == 1) {
 194         tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
 195     } else {
 196         tc->pcState(tc->readMiscReg(MISCREG_EBASE));
 197     }
 198 }
 199
 200 void
 201 TlbModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 202 {
 203     setTlbExceptionState(tc, 0x1);
 204
 205     tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
 206 }
 207
 208 void
 209 SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 210 {
 211     DPRINTF(MipsPRA, "%s encountered.\n", name());
 212     setExceptionState(tc, 0x8);
 213
 214     tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
 215 }
 216
 217 void
 218 InterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 219 {
 220     DPRINTF(MipsPRA, "%s encountered.\n", name());
 221     setExceptionState(tc, 0x0A);
 222
 223     CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
 224     if (cause.iv) {
 225         // Offset 200 for release 2
 226         tc->pcState(0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE));
 227     } else {
 228         //Ofset at 180 for release 1
 229         tc->pcState(vect() + tc->readMiscRegNoEffect(MISCREG_EBASE));
 230     }
 231 }
 232
 233 #endif // FULL_SYSTEM
 234
 235 void
 236 ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 237 {
 238 #if FULL_SYSTEM
 239     DPRINTF(MipsPRA, "%s encountered.\n", name());
 240     /* All reset activity must be invoked from here */
 241     tc->pcState(vect());
 242     DPRINTF(MipsPRA, "ResetFault::invoke : PC set to %x", tc->readPC());
 243 #endif
 244
 245     // Set Coprocessor 1 (Floating Point) To Usable
 246     StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
 247     status.cu.cu1 = 1;
 248     tc->setMiscReg(MISCREG_STATUS, status);
 249 }
 250
 251 void
 252 ReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 253 {
 254 #if  FULL_SYSTEM
 255     DPRINTF(MipsPRA, "%s encountered.\n", name());
 256     setExceptionState(tc, 0x0A);
 257     tc->pcState(vect() + tc->readMiscRegNoEffect(MISCREG_EBASE));
 258 #else
 259     panic("%s encountered.\n", name());
 260 #endif
 261 }
 262
 263 void
 264 ThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 265 {
 266     DPRINTF(MipsPRA, "%s encountered.\n", name());
 267     panic("%s encountered.\n", name());
 268 }
 269
 270 void
 271 DspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 272 {
 273     DPRINTF(MipsPRA, "%s encountered.\n", name());
 274     panic("%s encountered.\n", name());
 275 }
 276
 277 void
 278 CoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 279 {
 280 #if FULL_SYSTEM
 281     DPRINTF(MipsPRA, "%s encountered.\n", name());
 282     setExceptionState(tc, 0xb);
 283     // The ID of the coprocessor causing the exception is stored in
 284     // CoprocessorUnusableFault::coProcID
 285     CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
 286     cause.ce = coProcID;
 287     tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
 288     tc->pcState(vect() + tc->readMiscReg(MISCREG_EBASE));
 289 #else
 290     warn("%s (CP%d) encountered.\n", name(), coProcID);
 291 #endif
 292 }
 293
 294 } // namespace MipsISA
 295