src/arch/mips/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  */
  30
  31 #include "arch/mips/faults.hh"
  32 #include "cpu/thread_context.hh"
  33 #include "cpu/base.hh"
  34 #include "base/trace.hh"
  35 #if !FULL_SYSTEM
  36 #include "sim/process.hh"
  37 #include "mem/page_table.hh"
  38 #endif
  39
  40 namespace MipsISA
  41 {
  42
  43 FaultName MachineCheckFault::_name = "Machine Check";
  44 FaultVect MachineCheckFault::_vect = 0x0401;
  45 FaultStat MachineCheckFault::_count;
  46
  47 FaultName AlignmentFault::_name = "Alignment";
  48 FaultVect AlignmentFault::_vect = 0x0301;
  49 FaultStat AlignmentFault::_count;
  50
  51 FaultName ResetFault::_name = "reset";
  52 FaultVect ResetFault::_vect = 0x0001;
  53 FaultStat ResetFault::_count;
  54
  55 FaultName ArithmeticFault::_name = "arith";
  56 FaultVect ArithmeticFault::_vect = 0x0501;
  57 FaultStat ArithmeticFault::_count;
  58
  59 #if !FULL_SYSTEM
  60 FaultName PageTableFault::_name = "page_table_fault";
  61 FaultVect PageTableFault::_vect = 0x0000;
  62 FaultStat PageTableFault::_count;
  63 #endif
  64
  65 FaultName InterruptFault::_name = "interrupt";
  66 FaultVect InterruptFault::_vect = 0x0101;
  67 FaultStat InterruptFault::_count;
  68
  69 FaultName NDtbMissFault::_name = "dtb_miss_single";
  70 FaultVect NDtbMissFault::_vect = 0x0201;
  71 FaultStat NDtbMissFault::_count;
  72
  73 FaultName PDtbMissFault::_name = "dtb_miss_double";
  74 FaultVect PDtbMissFault::_vect = 0x0281;
  75 FaultStat PDtbMissFault::_count;
  76
  77 FaultName DtbPageFault::_name = "dfault";
  78 FaultVect DtbPageFault::_vect = 0x0381;
  79 FaultStat DtbPageFault::_count;
  80
  81 FaultName DtbAcvFault::_name = "dfault";
  82 FaultVect DtbAcvFault::_vect = 0x0381;
  83 FaultStat DtbAcvFault::_count;
  84
  85 FaultName ItbMissFault::_name = "itbmiss";
  86 FaultVect ItbMissFault::_vect = 0x0181;
  87 FaultStat ItbMissFault::_count;
  88
  89 FaultName ItbPageFault::_name = "itbmiss";
  90 FaultVect ItbPageFault::_vect = 0x0181;
  91 FaultStat ItbPageFault::_count;
  92
  93 FaultName ItbAcvFault::_name = "iaccvio";
  94 FaultVect ItbAcvFault::_vect = 0x0081;
  95 FaultStat ItbAcvFault::_count;
  96
  97 FaultName UnimplementedOpcodeFault::_name = "opdec";
  98 FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
  99 FaultStat UnimplementedOpcodeFault::_count;
 100
 101 FaultName FloatEnableFault::_name = "fen";
 102 FaultVect FloatEnableFault::_vect = 0x0581;
 103 FaultStat FloatEnableFault::_count;
 104
 105 FaultName PalFault::_name = "pal";
 106 FaultVect PalFault::_vect = 0x2001;
 107 FaultStat PalFault::_count;
 108
 109 FaultName IntegerOverflowFault::_name = "intover";
 110 FaultVect IntegerOverflowFault::_vect = 0x0501;
 111 FaultStat IntegerOverflowFault::_count;
 112
 113 #if FULL_SYSTEM
 114
 115 void MipsFault::invoke(ThreadContext * tc)
 116 {
 117     FaultBase::invoke(tc);
 118     countStat()++;
 119
 120     // exception restart address
 121     if (setRestartAddress() || !tc->inPalMode())
 122         tc->setMiscReg(MipsISA::IPR_EXC_ADDR, tc->readPC());
 123
 124     if (skipFaultingInstruction()) {
 125         // traps...  skip faulting instruction.
 126         tc->setMiscReg(MipsISA::IPR_EXC_ADDR,
 127                    tc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
 128     }
 129
 130     tc->setPC(tc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
 131     tc->setNextPC(tc->readPC() + sizeof(MachInst));
 132 }
 133
 134 void ArithmeticFault::invoke(ThreadContext * tc)
 135 {
 136     FaultBase::invoke(tc);
 137     panic("Arithmetic traps are unimplemented!");
 138 }
 139
 140 #else //!FULL_SYSTEM
 141
 142 void PageTableFault::invoke(ThreadContext *tc)
 143 {
 144     Process *p = tc->getProcessPtr();
 145
 146     // address is higher than the stack region or in the current stack region
 147     if (vaddr > p->stack_base || vaddr > p->stack_min)
 148         FaultBase::invoke(tc);
 149
 150     // We've accessed the next page
 151     if (vaddr > p->stack_min - PageBytes) {
 152         p->stack_min -= PageBytes;
 153         if (p->stack_base - p->stack_min > 8*1024*1024)
 154             fatal("Over max stack size for one thread\n");
 155         p->pTable->allocate(p->stack_min, PageBytes);
 156         warn("Increasing stack size by one page.");
 157     } else {
 158         FaultBase::invoke(tc);
 159     }
 160 }
 161
 162 #endif
 163 } // namespace MipsISA
 164