src/arch/mips/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Korey Sewell
  30  */
  31
  32 #include "arch/mips/faults.hh"
  33 #include "cpu/thread_context.hh"
  34 #include "cpu/base.hh"
  35 #include "base/trace.hh"
  36
  37 #if !FULL_SYSTEM
  38 #include "sim/process.hh"
  39 #include "mem/page_table.hh"
  40 #endif
  41
  42 namespace MipsISA
  43 {
  44
  45 FaultName MachineCheckFault::_name = "Machine Check";
  46 FaultVect MachineCheckFault::_vect = 0x0401;
  47 FaultStat MachineCheckFault::_count;
  48
  49 FaultName AlignmentFault::_name = "Alignment";
  50 FaultVect AlignmentFault::_vect = 0x0301;
  51 FaultStat AlignmentFault::_count;
  52
  53 FaultName ResetFault::_name = "reset";
  54 FaultVect ResetFault::_vect = 0x0001;
  55 FaultStat ResetFault::_count;
  56
  57 FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable";
  58 FaultVect CoprocessorUnusableFault::_vect = 0xF001;
  59 FaultStat CoprocessorUnusableFault::_count;
  60
  61 FaultName ReservedInstructionFault::_name = "Reserved Instruction";
  62 FaultVect ReservedInstructionFault::_vect = 0x0F01;
  63 FaultStat ReservedInstructionFault::_count;
  64
  65 FaultName ThreadFault::_name = "thread";
  66 FaultVect ThreadFault::_vect = 0x00F1;
  67 FaultStat ThreadFault::_count;
  68
  69
  70 FaultName ArithmeticFault::_name = "arith";
  71 FaultVect ArithmeticFault::_vect = 0x0501;
  72 FaultStat ArithmeticFault::_count;
  73
  74 FaultName UnimplementedOpcodeFault::_name = "opdec";
  75 FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
  76 FaultStat UnimplementedOpcodeFault::_count;
  77
  78 FaultName InterruptFault::_name = "interrupt";
  79 FaultVect InterruptFault::_vect = 0x0101;
  80 FaultStat InterruptFault::_count;
  81
  82 FaultName NDtbMissFault::_name = "dtb_miss_single";
  83 FaultVect NDtbMissFault::_vect = 0x0201;
  84 FaultStat NDtbMissFault::_count;
  85
  86 FaultName PDtbMissFault::_name = "dtb_miss_double";
  87 FaultVect PDtbMissFault::_vect = 0x0281;
  88 FaultStat PDtbMissFault::_count;
  89
  90 FaultName DtbPageFault::_name = "dfault";
  91 FaultVect DtbPageFault::_vect = 0x0381;
  92 FaultStat DtbPageFault::_count;
  93
  94 FaultName DtbAcvFault::_name = "dfault";
  95 FaultVect DtbAcvFault::_vect = 0x0381;
  96 FaultStat DtbAcvFault::_count;
  97
  98 FaultName ItbMissFault::_name = "itbmiss";
  99 FaultVect ItbMissFault::_vect = 0x0181;
 100 FaultStat ItbMissFault::_count;
 101
 102 FaultName ItbPageFault::_name = "itbmiss";
 103 FaultVect ItbPageFault::_vect = 0x0181;
 104 FaultStat ItbPageFault::_count;
 105
 106 FaultName ItbAcvFault::_name = "iaccvio";
 107 FaultVect ItbAcvFault::_vect = 0x0081;
 108 FaultStat ItbAcvFault::_count;
 109
 110 FaultName FloatEnableFault::_name = "fen";
 111 FaultVect FloatEnableFault::_vect = 0x0581;
 112 FaultStat FloatEnableFault::_count;
 113
 114 FaultName IntegerOverflowFault::_name = "intover";
 115 FaultVect IntegerOverflowFault::_vect = 0x0501;
 116 FaultStat IntegerOverflowFault::_count;
 117
 118 FaultName DspStateDisabledFault::_name = "intover";
 119 FaultVect DspStateDisabledFault::_vect = 0x001a;
 120 FaultStat DspStateDisabledFault::_count;
 121
 122 void ResetFault::invoke(ThreadContext *tc)
 123 {
 124     warn("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
 125     //tc->getCpuPtr()->reset();
 126 }
 127
 128 void CoprocessorUnusableFault::invoke(ThreadContext *tc)
 129 {
 130     panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
 131 }
 132
 133 void ReservedInstructionFault::invoke(ThreadContext *tc)
 134 {
 135     panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
 136 }
 137
 138 void ThreadFault::invoke(ThreadContext *tc)
 139 {
 140     panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
 141 }
 142
 143 void DspStateDisabledFault::invoke(ThreadContext *tc)
 144 {
 145     panic("[tid:%i]: %s encountered.\n", tc->getThreadNum(), name());
 146 }
 147
 148 } // namespace MipsISA
 149