src/arch/mips/faults.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Korey Sewell
  30  */
  31
  32 #include "arch/mips/faults.hh"
  33 #include "cpu/thread_context.hh"
  34 #include "cpu/base.hh"
  35 #include "base/trace.hh"
  36
  37 #if !FULL_SYSTEM
  38 #include "sim/process.hh"
  39 #include "mem/page_table.hh"
  40 #endif
  41
  42 namespace MipsISA
  43 {
  44
  45 FaultName MachineCheckFault::_name = "Machine Check";
  46 FaultVect MachineCheckFault::_vect = 0x0401;
  47 FaultStat MachineCheckFault::_count;
  48
  49 FaultName AlignmentFault::_name = "Alignment";
  50 FaultVect AlignmentFault::_vect = 0x0301;
  51 FaultStat AlignmentFault::_count;
  52
  53 FaultName ResetFault::_name = "reset";
  54 FaultVect ResetFault::_vect = 0x0001;
  55 FaultStat ResetFault::_count;
  56
  57 FaultName ArithmeticFault::_name = "arith";
  58 FaultVect ArithmeticFault::_vect = 0x0501;
  59 FaultStat ArithmeticFault::_count;
  60
  61 #if !FULL_SYSTEM
  62 FaultName PageTableFault::_name = "page_table_fault";
  63 FaultVect PageTableFault::_vect = 0x0000;
  64 FaultStat PageTableFault::_count;
  65 #endif
  66
  67 FaultName InterruptFault::_name = "interrupt";
  68 FaultVect InterruptFault::_vect = 0x0101;
  69 FaultStat InterruptFault::_count;
  70
  71 FaultName NDtbMissFault::_name = "dtb_miss_single";
  72 FaultVect NDtbMissFault::_vect = 0x0201;
  73 FaultStat NDtbMissFault::_count;
  74
  75 FaultName PDtbMissFault::_name = "dtb_miss_double";
  76 FaultVect PDtbMissFault::_vect = 0x0281;
  77 FaultStat PDtbMissFault::_count;
  78
  79 FaultName DtbPageFault::_name = "dfault";
  80 FaultVect DtbPageFault::_vect = 0x0381;
  81 FaultStat DtbPageFault::_count;
  82
  83 FaultName DtbAcvFault::_name = "dfault";
  84 FaultVect DtbAcvFault::_vect = 0x0381;
  85 FaultStat DtbAcvFault::_count;
  86
  87 FaultName ItbMissFault::_name = "itbmiss";
  88 FaultVect ItbMissFault::_vect = 0x0181;
  89 FaultStat ItbMissFault::_count;
  90
  91 FaultName ItbPageFault::_name = "itbmiss";
  92 FaultVect ItbPageFault::_vect = 0x0181;
  93 FaultStat ItbPageFault::_count;
  94
  95 FaultName ItbAcvFault::_name = "iaccvio";
  96 FaultVect ItbAcvFault::_vect = 0x0081;
  97 FaultStat ItbAcvFault::_count;
  98
  99 FaultName UnimplementedOpcodeFault::_name = "opdec";
 100 FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
 101 FaultStat UnimplementedOpcodeFault::_count;
 102
 103 FaultName FloatEnableFault::_name = "fen";
 104 FaultVect FloatEnableFault::_vect = 0x0581;
 105 FaultStat FloatEnableFault::_count;
 106
 107 FaultName PalFault::_name = "pal";
 108 FaultVect PalFault::_vect = 0x2001;
 109 FaultStat PalFault::_count;
 110
 111 FaultName IntegerOverflowFault::_name = "intover";
 112 FaultVect IntegerOverflowFault::_vect = 0x0501;
 113 FaultStat IntegerOverflowFault::_count;
 114
 115 void PageTableFault::invoke(ThreadContext *tc)
 116 {
 117     Process *p = tc->getProcessPtr();
 118
 119     // address is higher than the stack region or in the current stack region
 120     if (vaddr > p->stack_base || vaddr > p->stack_min)
 121         FaultBase::invoke(tc);
 122
 123     // We've accessed the next page
 124     if (vaddr > p->stack_min - PageBytes) {
 125         p->stack_min -= PageBytes;
 126         if (p->stack_base - p->stack_min > 8*1024*1024)
 127             fatal("Over max stack size for one thread\n");
 128         p->pTable->allocate(p->stack_min, PageBytes);
 129         warn("Increasing stack size by one page.");
 130     } else {
 131         FaultBase::invoke(tc);
 132     }
 133 }
 134
 135 } // namespace MipsISA
 136