2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
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36 #ifndef __MIPS_FAULTS_HH__
37 #define __MIPS_FAULTS_HH__
39 #include "arch/mips/pra_constants.hh"
40 #include "cpu/thread_context.hh"
41 #include "debug/MipsPRA.hh"
42 #include "sim/faults.hh"
43 #include "sim/full_system.hh"
48 typedef const Addr FaultVect;
51 // A dummy value to use when the code isn't defined or doesn't matter.
76 class MipsFaultBase : public FaultBase
82 const FaultVect offset;
86 void setExceptionState(ThreadContext *, uint8_t);
88 virtual FaultVect offset(ThreadContext *tc) const = 0;
89 virtual ExcCode code() const = 0;
90 virtual FaultVect base(ThreadContext *tc) const
92 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
94 return tc->readMiscReg(MISCREG_EBASE);
100 vect(ThreadContext *tc) const
102 return base(tc) + offset(tc);
105 void invoke(ThreadContext * tc,
106 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
109 template <typename T>
110 class MipsFault : public MipsFaultBase
113 static FaultVals vals;
115 FaultName name() const { return vals.name; }
116 FaultVect offset(ThreadContext *tc) const { return vals.offset; }
117 ExcCode code() const { return vals.code; }
120 class SystemCallFault : public MipsFault<SystemCallFault> {};
121 class ReservedInstructionFault : public MipsFault<ReservedInstructionFault> {};
122 class ThreadFault : public MipsFault<ThreadFault> {};
123 class IntegerOverflowFault : public MipsFault<IntegerOverflowFault> {};
124 class TrapFault : public MipsFault<TrapFault> {};
125 class BreakpointFault : public MipsFault<BreakpointFault> {};
126 class DspStateDisabledFault : public MipsFault<DspStateDisabledFault> {};
128 class MachineCheckFault : public MipsFault<MachineCheckFault>
131 bool isMachineCheckFault() { return true; }
134 class ResetFault : public MipsFault<ResetFault>
137 void invoke(ThreadContext * tc,
138 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
142 class SoftResetFault : public MipsFault<SoftResetFault>
145 void invoke(ThreadContext * tc,
146 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
149 class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
152 void invoke(ThreadContext * tc,
153 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
156 class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
161 CoprocessorUnusableFault(int _procid) : coProcID(_procid)
165 invoke(ThreadContext * tc,
166 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
168 MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
170 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
172 tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
177 class InterruptFault : public MipsFault<InterruptFault>
181 offset(ThreadContext *tc) const
183 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
184 // offset 0x200 for release 2, 0x180 for release 1.
185 return cause.iv ? 0x200 : 0x180;
189 template <typename T>
190 class AddressFault : public MipsFault<T>
196 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
200 invoke(ThreadContext * tc,
201 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
203 MipsFault<T>::invoke(tc, inst);
205 tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
209 class AddressErrorFault : public AddressFault<AddressErrorFault>
212 AddressErrorFault(Addr _vaddr, bool _store) :
213 AddressFault<AddressErrorFault>(_vaddr, _store)
219 return store ? ExcCodeAdES : ExcCodeAdEL;
224 template <typename T>
225 class TlbFault : public AddressFault<T>
231 TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) :
232 AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn)
236 setTlbExceptionState(ThreadContext *tc, uint8_t excCode)
238 this->setExceptionState(tc, excCode);
240 tc->setMiscRegNoEffect(MISCREG_BADVADDR, this->vaddr);
241 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
242 entryHi.asid = this->asid;
243 entryHi.vpn2 = this->vpn >> 2;
244 entryHi.vpn2x = this->vpn & 0x3;
245 tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
247 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
248 context.badVPN2 = this->vpn >> 2;
249 tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
253 invoke(ThreadContext * tc,
254 StaticInstPtr inst = StaticInst::nullStaticInstPtr)
257 DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
258 Addr vect = this->vect(tc);
259 setTlbExceptionState(tc, this->code());
262 AddressFault<T>::invoke(tc, inst);
269 return this->store ? ExcCodeTlbS : ExcCodeTlbL;
273 class TlbRefillFault : public TlbFault<TlbRefillFault>
276 TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
277 TlbFault<TlbRefillFault>(asid, vaddr, vpn, store)
281 offset(ThreadContext *tc) const
283 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
284 return status.exl ? 0x180 : 0x000;
288 class TlbInvalidFault : public TlbFault<TlbInvalidFault>
291 TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) :
292 TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store)
296 class TlbModifiedFault : public TlbFault<TlbModifiedFault>
299 TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn) :
300 TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false)
303 ExcCode code() const { return MipsFault<TlbModifiedFault>::code(); }
306 } // namespace MipsISA
308 #endif // __MIPS_FAULTS_HH__