src/arch/mips/interrupts.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Rick Strong
  29  */
  30
  31 #ifndef __ARCH_MIPS_INTERRUPT_HH__
  32 #define __ARCH_MIPS_INTERRUPT_HH__
  33
  34 #include <string>
  35
  36 #include "arch/mips/faults.hh"
  37 #include "base/compiler.hh"
  38 #include "base/misc.hh"
  39 #include "params/MipsInterrupts.hh"
  40 #include "sim/serialize.hh"
  41 #include "sim/sim_object.hh"
  42
  43 class BaseCPU;
  44 class Checkpoint;
  45
  46 namespace MipsISA
  47 {
  48
  49 class Interrupts : public SimObject
  50 {
  51   public:
  52     typedef MipsInterruptsParams Params;
  53
  54     const Params *
  55     params() const
  56     {
  57         return dynamic_cast<const Params *>(_params);
  58     }
  59
  60     Interrupts(Params * p) : SimObject(p)
  61     {
  62         newInfoSet = false;
  63     }
  64
  65     void
  66     setCPU(BaseCPU *_cpu)
  67     {}
  68
  69     //  post(int int_num, int index) is responsible
  70     //  for posting an interrupt. It sets a bit
  71     //  in intstatus corresponding to Cause IP*. The
  72     //  MIPS register Cause is updated by updateIntrInfo
  73     //  which is called by checkInterrupts
  74     //
  75     void post(int int_num, ThreadContext *tc);
  76     void post(int int_num, int index);
  77
  78     // clear(int int_num, int index) is responsible
  79     //  for clearing an interrupt. It clear a bit
  80     //  in intstatus corresponding to Cause IP*. The
  81     //  MIPS register Cause is updated by updateIntrInfo
  82     //  which is called by checkInterrupts
  83     //
  84     void clear(int int_num, ThreadContext* tc);
  85     void clear(int int_num, int index);
  86
  87     //  clearAll() is responsible
  88     //  for clearing all interrupts. It clears all bits
  89     //  in intstatus corresponding to Cause IP*. The
  90     //  MIPS register Cause is updated by updateIntrInfo
  91     //  which is called by checkInterrupts
  92     //
  93     void clearAll(ThreadContext *tc);
  94     void clearAll();
  95
  96     // getInterrupt(ThreadContext * tc) checks if an interrupt
  97     //  should be returned. It ands the interrupt mask and
  98     //  and interrupt pending bits to see if one exists. It
  99     //  also makes sure interrupts are enabled (IE) and
 100     //  that ERL and ERX are not set
 101     //
 102     Fault getInterrupt(ThreadContext *tc);
 103
 104     // updateIntrInfo(ThreadContext *tc) const syncs the
 105     //  MIPS cause register with the instatus variable. instatus
 106     //  is essentially a copy of the MIPS cause[IP7:IP0]
 107     //
 108     void updateIntrInfo(ThreadContext *tc) const;
 109     bool interruptsPending(ThreadContext *tc) const;
 110     bool onCpuTimerInterrupt(ThreadContext *tc) const;
 111
 112     bool
 113     checkInterrupts(ThreadContext *tc) const
 114     {
 115         return interruptsPending(tc);
 116     }
 117
 118
 119     void
 120     serialize(std::ostream &os)
 121     {
 122         fatal("Serialization of Interrupts Unimplemented for MIPS");
 123     }
 124
 125     void
 126     unserialize(Checkpoint *cp, const std::string &section)
 127     {
 128         fatal("Unserialization of Interrupts Unimplemented for MIPS");
 129     }
 130
 131   private:
 132     bool newInfoSet;
 133     int newIpl;
 134     int newSummary;
 135 };
 136
 137 }
 138
 139 #endif
 140