2 * Copyright (c) 2007 MIPS Technologies, Inc.
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6 * modification, are permitted provided that the following conditions are
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9 * redistributions in binary form must reproduce the above copyright
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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28 * Authors: Rick Strong
31 #ifndef __ARCH_MIPS_INTERRUPT_HH__
32 #define __ARCH_MIPS_INTERRUPT_HH__
36 #include "arch/mips/faults.hh"
37 #include "base/compiler.hh"
38 #include "base/misc.hh"
39 #include "params/MipsInterrupts.hh"
40 #include "sim/serialize.hh"
41 #include "sim/sim_object.hh"
49 class Interrupts : public SimObject
52 typedef MipsInterruptsParams Params;
57 return dynamic_cast<const Params *>(_params);
60 Interrupts(Params * p) : SimObject(p)
69 // post(int int_num, int index) is responsible
70 // for posting an interrupt. It sets a bit
71 // in intstatus corresponding to Cause IP*. The
72 // MIPS register Cause is updated by updateIntrInfo
73 // which is called by checkInterrupts
75 void post(int int_num, ThreadContext *tc);
76 void post(int int_num, int index);
78 // clear(int int_num, int index) is responsible
79 // for clearing an interrupt. It clear a bit
80 // in intstatus corresponding to Cause IP*. The
81 // MIPS register Cause is updated by updateIntrInfo
82 // which is called by checkInterrupts
84 void clear(int int_num, ThreadContext* tc);
85 void clear(int int_num, int index);
87 // clearAll() is responsible
88 // for clearing all interrupts. It clears all bits
89 // in intstatus corresponding to Cause IP*. The
90 // MIPS register Cause is updated by updateIntrInfo
91 // which is called by checkInterrupts
93 void clearAll(ThreadContext *tc);
96 // getInterrupt(ThreadContext * tc) checks if an interrupt
97 // should be returned. It ands the interrupt mask and
98 // and interrupt pending bits to see if one exists. It
99 // also makes sure interrupts are enabled (IE) and
100 // that ERL and ERX are not set
102 Fault getInterrupt(ThreadContext *tc);
104 // updateIntrInfo(ThreadContext *tc) const syncs the
105 // MIPS cause register with the instatus variable. instatus
106 // is essentially a copy of the MIPS cause[IP7:IP0]
108 void updateIntrInfo(ThreadContext *tc) const;
109 bool interruptsPending(ThreadContext *tc) const;
110 bool onCpuTimerInterrupt(ThreadContext *tc) const;
113 checkInterrupts(ThreadContext *tc) const
115 return interruptsPending(tc);
120 serialize(std::ostream &os)
122 fatal("Serialization of Interrupts Unimplemented for MIPS");
126 unserialize(Checkpoint *cp, const std::string §ion)
128 fatal("Unserialization of Interrupts Unimplemented for MIPS");