src/arch/mips/interrupts.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Rick Strong
  29  */
  30
  31 #ifndef __ARCH_MIPS_INTERRUPT_HH__
  32 #define __ARCH_MIPS_INTERRUPT_HH__
  33
  34 #include <string>
  35
  36 #include "arch/generic/interrupts.hh"
  37 #include "arch/mips/faults.hh"
  38 #include "base/compiler.hh"
  39 #include "base/logging.hh"
  40 #include "params/MipsInterrupts.hh"
  41 #include "sim/serialize.hh"
  42
  43 class BaseCPU;
  44 class Checkpoint;
  45
  46 namespace MipsISA
  47 {
  48
  49 class Interrupts : public BaseInterrupts
  50 {
  51   public:
  52     typedef MipsInterruptsParams Params;
  53
  54     const Params *
  55     params() const
  56     {
  57         return dynamic_cast<const Params *>(_params);
  58     }
  59
  60     Interrupts(Params * p) : BaseInterrupts(p)
  61     {
  62     }
  63
  64     void setCPU(BaseCPU *_cpu) override {}
  65
  66     //  post(int int_num, int index) is responsible
  67     //  for posting an interrupt. It sets a bit
  68     //  in intstatus corresponding to Cause IP*. The
  69     //  MIPS register Cause is updated by updateIntrInfo
  70     //  which is called by checkInterrupts
  71     //
  72     void post(int int_num, ThreadContext *tc);
  73     void post(int int_num, int index) override;
  74
  75     // clear(int int_num, int index) is responsible
  76     //  for clearing an interrupt. It clear a bit
  77     //  in intstatus corresponding to Cause IP*. The
  78     //  MIPS register Cause is updated by updateIntrInfo
  79     //  which is called by checkInterrupts
  80     //
  81     void clear(int int_num, ThreadContext* tc);
  82     void clear(int int_num, int index) override;
  83
  84     //  clearAll() is responsible
  85     //  for clearing all interrupts. It clears all bits
  86     //  in intstatus corresponding to Cause IP*. The
  87     //  MIPS register Cause is updated by updateIntrInfo
  88     //  which is called by checkInterrupts
  89     //
  90     void clearAll(ThreadContext *tc);
  91     void clearAll() override;
  92
  93     // getInterrupt(ThreadContext * tc) checks if an interrupt
  94     //  should be returned. It ands the interrupt mask and
  95     //  and interrupt pending bits to see if one exists. It
  96     //  also makes sure interrupts are enabled (IE) and
  97     //  that ERL and ERX are not set
  98     //
  99     Fault getInterrupt(ThreadContext *tc) override;
 100
 101     // updateIntrInfo(ThreadContext *tc) const syncs the
 102     //  MIPS cause register with the instatus variable. instatus
 103     //  is essentially a copy of the MIPS cause[IP7:IP0]
 104     //
 105     void updateIntrInfo(ThreadContext *tc) override;
 106     bool interruptsPending(ThreadContext *tc) const;
 107     bool onCpuTimerInterrupt(ThreadContext *tc) const;
 108     bool checkInterrupts(ThreadContext *tc) const override;
 109
 110     void
 111     serialize(CheckpointOut &cp) const override
 112     {
 113         fatal("Serialization of Interrupts Unimplemented for MIPS");
 114     }
 115
 116     void
 117     unserialize(CheckpointIn &cp) override
 118     {
 119         fatal("Unserialization of Interrupts Unimplemented for MIPS");
 120     }
 121 };
 122
 123 }
 124
 125 #endif
 126