src/arch/mips/interrupts.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Rick Strong
  29  */
  30
  31 #ifndef __ARCH_MIPS_INTERRUPT_HH__
  32 #define __ARCH_MIPS_INTERRUPT_HH__
  33
  34 #include <string>
  35
  36 #include "arch/mips/faults.hh"
  37 #include "base/compiler.hh"
  38 #include "base/misc.hh"
  39 #include "params/MipsInterrupts.hh"
  40 #include "sim/serialize.hh"
  41 #include "sim/sim_object.hh"
  42
  43 class BaseCPU;
  44 class Checkpoint;
  45
  46 namespace MipsISA
  47 {
  48
  49 class Interrupts : public SimObject
  50 {
  51   public:
  52     typedef MipsInterruptsParams Params;
  53
  54     const Params *
  55     params() const
  56     {
  57         return dynamic_cast<const Params *>(_params);
  58     }
  59
  60     Interrupts(Params * p) : SimObject(p)
  61     {
  62     }
  63
  64     void
  65     setCPU(BaseCPU *_cpu)
  66     {}
  67
  68     //  post(int int_num, int index) is responsible
  69     //  for posting an interrupt. It sets a bit
  70     //  in intstatus corresponding to Cause IP*. The
  71     //  MIPS register Cause is updated by updateIntrInfo
  72     //  which is called by checkInterrupts
  73     //
  74     void post(int int_num, ThreadContext *tc);
  75     void post(int int_num, int index);
  76
  77     // clear(int int_num, int index) is responsible
  78     //  for clearing an interrupt. It clear a bit
  79     //  in intstatus corresponding to Cause IP*. The
  80     //  MIPS register Cause is updated by updateIntrInfo
  81     //  which is called by checkInterrupts
  82     //
  83     void clear(int int_num, ThreadContext* tc);
  84     void clear(int int_num, int index);
  85
  86     //  clearAll() is responsible
  87     //  for clearing all interrupts. It clears all bits
  88     //  in intstatus corresponding to Cause IP*. The
  89     //  MIPS register Cause is updated by updateIntrInfo
  90     //  which is called by checkInterrupts
  91     //
  92     void clearAll(ThreadContext *tc);
  93     void clearAll();
  94
  95     // getInterrupt(ThreadContext * tc) checks if an interrupt
  96     //  should be returned. It ands the interrupt mask and
  97     //  and interrupt pending bits to see if one exists. It
  98     //  also makes sure interrupts are enabled (IE) and
  99     //  that ERL and ERX are not set
 100     //
 101     Fault getInterrupt(ThreadContext *tc);
 102
 103     // updateIntrInfo(ThreadContext *tc) const syncs the
 104     //  MIPS cause register with the instatus variable. instatus
 105     //  is essentially a copy of the MIPS cause[IP7:IP0]
 106     //
 107     void updateIntrInfo(ThreadContext *tc) const;
 108     bool interruptsPending(ThreadContext *tc) const;
 109     bool onCpuTimerInterrupt(ThreadContext *tc) const;
 110
 111     bool
 112     checkInterrupts(ThreadContext *tc) const
 113     {
 114         return interruptsPending(tc);
 115     }
 116
 117
 118     void
 119     serialize(CheckpointOut &cp) const override
 120     {
 121         fatal("Serialization of Interrupts Unimplemented for MIPS");
 122     }
 123
 124     void
 125     unserialize(CheckpointIn &cp) override
 126     {
 127         fatal("Unserialization of Interrupts Unimplemented for MIPS");
 128     }
 129 };
 130
 131 }
 132
 133 #endif
 134