2 * Copyright (c) 2007 MIPS Technologies, Inc.
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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28 * Authors: Rick Strong
31 #ifndef __ARCH_MIPS_INTERRUPT_HH__
32 #define __ARCH_MIPS_INTERRUPT_HH__
35 #include "arch/mips/faults.hh"
36 #include "base/compiler.hh"
53 oncputimerintr = false;
56 // post(int int_num, int index) is responsible
57 // for posting an interrupt. It sets a bit
58 // in intstatus corresponding to Cause IP*. The
59 // MIPS register Cause is updated by updateIntrInfo
60 // which is called by check_interrupts
62 void post(int int_num, int index);
63 // clear(int int_num, int index) is responsible
64 // for clearing an interrupt. It clear a bit
65 // in intstatus corresponding to Cause IP*. The
66 // MIPS register Cause is updated by updateIntrInfo
67 // which is called by check_interrupts
69 void clear(int int_num, int index);
70 // clear_all() is responsible
71 // for clearing all interrupts. It clears all bits
72 // in intstatus corresponding to Cause IP*. The
73 // MIPS register Cause is updated by updateIntrInfo
74 // which is called by check_interrupts
78 // getInterrupt(ThreadContext * tc) checks if an interrupt
79 // should be returned. It ands the interrupt mask and
80 // and interrupt pending bits to see if one exists. It
81 // also makes sure interrupts are enabled (IE) and
82 // that ERL and ERX are not set
84 Fault getInterrupt(ThreadContext * tc);
86 // updateIntrInfo(ThreadContext *tc) const syncs the
87 // MIPS cause register with the instatus variable. instatus
88 // is essentially a copy of the MIPS cause[IP7:IP0]
90 void updateIntrInfo(ThreadContext *tc) const;
91 void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
92 bool onCpuTimerInterrupt(ThreadContext *tc) const;
94 bool check_interrupts(ThreadContext * tc) const{
95 //return (intstatus != 0) && !(tc->readPC() & 0x3);
96 if (oncputimerintr == false){
98 return ((intstatus != 0) || onCpuTimerInterrupt(tc));
109 //bool oncputimerintr;
115 //oncputimerintr = false;
118 // post(int int_num, int index) is responsible
119 // for posting an interrupt. It sets a bit
120 // in intstatus corresponding to Cause IP*. The
121 // MIPS register Cause is updated by updateIntrInfo
122 // which is called by check_interrupts
124 void post(int int_num, ThreadContext* tc);
125 void post(int int_num, int index);
127 // clear(int int_num, int index) is responsible
128 // for clearing an interrupt. It clear a bit
129 // in intstatus corresponding to Cause IP*. The
130 // MIPS register Cause is updated by updateIntrInfo
131 // which is called by check_interrupts
133 void clear(int int_num, ThreadContext* tc);
134 void clear(int int_num, int index);
136 // clear_all() is responsible
137 // for clearing all interrupts. It clears all bits
138 // in intstatus corresponding to Cause IP*. The
139 // MIPS register Cause is updated by updateIntrInfo
140 // which is called by check_interrupts
142 void clear_all(ThreadContext* tc);
145 // getInterrupt(ThreadContext * tc) checks if an interrupt
146 // should be returned. It ands the interrupt mask and
147 // and interrupt pending bits to see if one exists. It
148 // also makes sure interrupts are enabled (IE) and
149 // that ERL and ERX are not set
151 Fault getInterrupt(ThreadContext * tc);
153 // updateIntrInfo(ThreadContext *tc) const syncs the
154 // MIPS cause register with the instatus variable. instatus
155 // is essentially a copy of the MIPS cause[IP7:IP0]
157 void updateIntrInfo(ThreadContext *tc) const;
158 bool interruptsPending(ThreadContext *tc) const;
159 bool onCpuTimerInterrupt(ThreadContext *tc) const;
161 bool check_interrupts(ThreadContext * tc) const{
162 return interruptsPending(tc);
166 void serialize(std::ostream &os)
168 fatal("Serialization of Interrupts Unimplemented for MIPS");
169 //SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
170 //SERIALIZE_SCALAR(intstatus);
173 void unserialize(Checkpoint *cp, const std::string §ion)
175 fatal("Unserialization of Interrupts Unimplemented for MIPS");
176 //UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
177 //UNSERIALIZE_SCALAR(intstatus);