src/arch/mips/isa/bitfields.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright \e.A\eN) 2007 MIPS Technologies, Inc.  All Rights Reserved
   4
   5 //  This software is part of the M5 simulator.
   6
   7 //  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
   8 //  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
   9 //  TO THESE TERMS AND CONDITIONS.
  10
  11 //  Permission is granted to use, copy, create derivative works and
  12 //  distribute this software and such derivative works for any purpose,
  13 //  so long as (1) the copyright notice above, this grant of permission,
  14 //  and the disclaimer below appear in all copies and derivative works
  15 //  made, (2) the copyright notice above is augmented as appropriate to
  16 //  reflect the addition of any new copyrightable work in a derivative
  17 //  work (e.g., Copyright \e.A\eN) <Publication Year> Copyright Owner), and (3)
  18 //  the name of MIPS Technologies, Inc. (\e$B!H\e(BMIPS\e$B!I\e(B) is not used in any
  19 //  advertising or publicity pertaining to the use or distribution of
  20 //  this software without specific, written prior authorization.
  21
  22 //  THIS SOFTWARE IS PROVIDED \e$B!H\e(BAS IS.\e$B!I\e(B  MIPS MAKES NO WARRANTIES AND
  23 //  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
  24 //  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25 //  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
  26 //  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
  27 //  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
  28 //  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
  29 //  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
  30 //  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
  31 //  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
  32 //  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
  33 //  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
  34
  35 //Authors: Korey L. Sewell
  36 //         Jaidev Patwardhan
  37
  38
  39 ////////////////////////////////////////////////////////////////////
  40 //
  41 // Bitfield definitions.
  42 //
  43
  44 def bitfield OPCODE     <31:26>;
  45 def bitfield OPCODE_HI  <31:29>;
  46 def bitfield OPCODE_LO  <28:26>;
  47
  48 def bitfield REGIMM      <20:16>;
  49 def bitfield REGIMM_HI   <20:19>;
  50 def bitfield REGIMM_LO   <18:16>;
  51
  52 def bitfield FUNCTION      < 5: 0>;
  53 def bitfield FUNCTION_HI   < 5: 3>;
  54 def bitfield FUNCTION_LO   < 2: 0>;
  55
  56 def bitfield RS       <25:21>;
  57 def bitfield RS_MSB   <25:25>;
  58 def bitfield RS_HI    <25:24>;
  59 def bitfield RS_LO    <23:21>;
  60 def bitfield RS_SRL   <25:22>;
  61 def bitfield RS_RT    <25:16>;
  62 def bitfield RT       <20:16>;
  63 def bitfield RT_HI    <20:19>;
  64 def bitfield RT_LO    <18:16>;
  65 def bitfield RT_RD    <20:11>;
  66 def bitfield RD       <15:11>;
  67
  68 def bitfield INTIMM       <15: 0>;
  69 def bitfield RS_RT_INTIMM <25: 0>;
  70
  71 // Floating-point operate format
  72 def bitfield FMT      <25:21>;
  73 def bitfield FR       <25:21>;
  74 def bitfield FT       <20:16>;
  75 def bitfield FS       <15:11>;
  76 def bitfield FD       <10:6>;
  77
  78 def bitfield ND       <17:17>;
  79 def bitfield TF       <16:16>;
  80 def bitfield MOVCI    <16:16>;
  81 def bitfield MOVCF    <16:16>;
  82 def bitfield SRL      <21:21>;
  83 def bitfield SRLV     < 6: 6>;
  84 def bitfield SA       <10: 6>;
  85
  86 // Floating Point Condition Codes
  87 def bitfield CC <10:8>;
  88 def bitfield BRANCH_CC <20:18>;
  89
  90 // CP0 Register Select
  91 def bitfield SEL       < 2: 0>;
  92
  93 // INTERRUPTS
  94 def bitfield SC       < 5: 5>;
  95
  96 // Branch format
  97 def bitfield OFFSET <15: 0>; // displacement
  98
  99 // Jmp format
 100 def bitfield JMPTARG    <25: 0>;
 101 def bitfield HINT       <10: 6>;
 102
 103 def bitfield SYSCALLCODE <25: 6>;
 104 def bitfield TRAPCODE    <15:13>;
 105
 106 // EXT/INS instructions
 107 def bitfield MSB        <15:11>;
 108 def bitfield LSB        <10: 6>;
 109
 110 // M5 instructions
 111 def bitfield M5FUNC <7:0>;
 112
 113 // DSP instructions
 114 def bitfield OP        <10:6>;
 115 def bitfield OP_HI     <10:9>;
 116 def bitfield OP_LO     <8:6>;
 117 def bitfield DSPSA     <23:21>;
 118 def bitfield HILOSA    <25:20>;
 119 def bitfield RDDSPMASK <21:16>;
 120 def bitfield WRDSPMASK <16:11>;
 121 def bitfield ACSRC     <22:21>;
 122 def bitfield ACDST     <12:11>;
 123 def bitfield BP        <12:11>;
 124
 125 // MT Instructions
 126 def bitfield POS   <10: 6>;
 127 def bitfield MT_U     <5:5>;
 128 def bitfield MT_H     <4:4>;
 129
 130 //Cache Ops
 131 def bitfield CACHE_OP <20:16>;