Merge vm1.(none):/home/stever/bk/newmem-head
[gem5.git] / src / arch / mips / isa / bitfields.isa
1 // -*- mode:c++ -*-
2
3 // Copyright (c) 2006 The Regents of The University of Michigan
4 // All rights reserved.
5 //
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
16 //
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 //
29 // Authors: Korey Sewell
30
31 //@TODO: Make sure the naming convention is consistent here.
32 ////////////////////////////////////////////////////////////////////
33 //
34 // Bitfield definitions.
35 //
36
37 def bitfield OPCODE <31:26>;
38 def bitfield OPCODE_HI <31:29>;
39 def bitfield OPCODE_LO <28:26>;
40
41 def bitfield REGIMM <20:16>;
42 def bitfield REGIMM_HI <20:19>;
43 def bitfield REGIMM_LO <18:16>;
44
45 def bitfield FUNCTION < 5: 0>;
46 def bitfield FUNCTION_HI < 5: 3>;
47 def bitfield FUNCTION_LO < 2: 0>;
48
49 def bitfield RS <25:21>;
50 def bitfield RS_MSB <25:25>;
51 def bitfield RS_HI <25:24>;
52 def bitfield RS_LO <23:21>;
53 def bitfield RS_SRL <25:22>;
54 def bitfield RS_RT <25:16>;
55 def bitfield RT <20:16>;
56 def bitfield RT_HI <20:19>;
57 def bitfield RT_LO <18:16>;
58 def bitfield RT_RD <20:11>;
59 def bitfield RD <15:11>;
60
61 def bitfield INTIMM <15: 0>;
62 def bitfield RS_RT_INTIMM <25: 0>;
63
64 // Floating-point operate format
65 def bitfield FMT <25:21>;
66 def bitfield FR <25:21>;
67 def bitfield FT <20:16>;
68 def bitfield FS <15:11>;
69 def bitfield FD <10:6>;
70
71 def bitfield ND <17:17>;
72 def bitfield TF <16:16>;
73 def bitfield MOVCI <16:16>;
74 def bitfield MOVCF <16:16>;
75 def bitfield SRL <21:21>;
76 def bitfield SRLV < 6: 6>;
77 def bitfield SA <10: 6>;
78
79 // Floating Point Condition Codes
80 def bitfield CC <10:8>;
81 def bitfield BRANCH_CC <20:18>;
82
83 // CP0 Register Select
84 def bitfield SEL < 2: 0>;
85
86 // INTERRUPTS
87 def bitfield SC < 5: 5>;
88
89 // Branch format
90 def bitfield OFFSET <15: 0>; // displacement
91
92 // Jmp format
93 def bitfield JMPTARG <25: 0>;
94 def bitfield HINT <10: 6>;
95
96 def bitfield SYSCALLCODE <25: 6>;
97 def bitfield TRAPCODE <15:13>;
98
99 // EXT/INS instructions
100 def bitfield MSB <15:11>;
101 def bitfield LSB <10: 6>;
102
103 // M5 instructions
104 def bitfield M5FUNC <7:0>;
105
106 // DSP instructions
107 def bitfield OP <10:6>;
108 def bitfield OP_HI <10:9>;
109 def bitfield OP_LO <8:6>;
110 def bitfield DSPSA <23:21>;
111 def bitfield HILOSA <25:20>;
112 def bitfield RDDSPMASK <21:16>;
113 def bitfield WRDSPMASK <16:11>;
114 def bitfield ACSRC <22:21>;
115 def bitfield ACDST <12:11>;
116 def bitfield BP <12:11>;
117
118 // MT Instructions
119 def bitfield POS <10: 6>;
120 def bitfield MT_U <5:5>;
121 def bitfield MT_H <4:4>;