src/arch/mips/isa/bitfields.isa

   1 // -*- mode:c++ -*-
   2
   3 ////////////////////////////////////////////////////////////////////
   4 //
   5 // Bitfield definitions.
   6 //
   7
   8 def bitfield OPCODE     <31:26>;
   9 def bitfield OPCODE_HI  <31:29>;
  10 def bitfield OPCODE_LO  <28:26>;
  11
  12 def bitfield REGIMM      <20:16>;
  13 def bitfield REGIMM_HI   <20:19>;
  14 def bitfield REGIMM_LO   <18:16>;
  15
  16 def bitfield FUNCTION      < 5: 0>;
  17 def bitfield FUNCTION_HI   < 5: 3>;
  18 def bitfield FUNCTION_LO   < 2: 0>;
  19
  20 // Integer operate format
  21 def bitfield RT       <20:16>;
  22 def bitfield RT_HI    <20:19>;
  23 def bitfield RT_LO    <18:16>;
  24
  25 def bitfield RS       <25:21>;
  26 def bitfield RS_MSB   <25:25>;
  27 def bitfield RS_HI    <25:24>;
  28 def bitfield RS_LO    <23:21>;
  29 def bitfield RS_SRL    <25:22>;
  30
  31 def bitfield RD       <15:11>;
  32
  33 def bitfield INTIMM     <15: 0>; // integer immediate (literal)
  34
  35 // Floating-point operate format
  36 def bitfield FMT      <25:21>;
  37 def bitfield FR       <25:21>;
  38 def bitfield FT       <20:16>;
  39 def bitfield FS       <15:11>;
  40 def bitfield FD       <10:6>;
  41
  42 def bitfield ND       <17:17>;
  43 def bitfield TF       <16:16>;
  44 def bitfield MOVCI    <16:16>;
  45 def bitfield MOVCF    <16:16>;
  46 def bitfield SRL      <21:21>;
  47 def bitfield SRLV     < 6: 6>;
  48 def bitfield SA       <10: 6>;
  49
  50 // Floating Point Condition Codes
  51 def bitfield CC <10:8>;
  52 def bitfield BRANCH_CC <20:18>;
  53
  54 // CP0 Register Select
  55 def bitfield SEL       < 2: 0>;
  56
  57 // Interrupts
  58 def bitfield SC       < 5: 5>;
  59
  60 // Branch format
  61 def bitfield OFFSET <15: 0>; // displacement
  62
  63 // Jmp format
  64 def bitfield JMPTARG    <25: 0>;
  65 def bitfield HINT       <10: 6>;
  66
  67 def bitfield SYSCALLCODE <25: 6>;
  68 def bitfield TRAPCODE    <15:13>;
  69
  70 // M5 instructions
  71 def bitfield M5FUNC <7:0>;