projects / gem5.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
mips,cpu: Get rid of the IsERET StaticInst flag.
[gem5.git] / src / arch / mips / isa / decoder.isa
1 // -*- mode:c++ -*-
2
3 // Copyright (c) 2007 MIPS Technologies, Inc.
4 // All rights reserved.
5 //
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
16 //
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
29 ////////////////////////////////////////////////////////////////////
30 //
31 // The actual MIPS32 ISA decoder
32 // -----------------------------
33 // The following instructions are specified in the MIPS32 ISA
34 // Specification. Decoding closely follows the style specified
35 // in the MIPS32 ISA specification document starting with Table
36 // A-2 (document available @ http://www.mips.com)
37 //
38 decode OPCODE_HI default Unknown::unknown() {
39 //Table A-2
40 0x0: decode OPCODE_LO {
41 0x0: decode FUNCTION_HI {
42 0x0: decode FUNCTION_LO {
43 0x1: decode MOVCI {
44 format BasicOp {
45 0: movf({{
46 Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs;
47 }});
48 1: movt({{
49 Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs;
50 }});
51 }
52 }
53
54 format BasicOp {
55 //Table A-3 Note: "Specific encodings of the rd, rs, and
56 //rt fields are used to distinguish SLL, SSNOP, and EHB
57 //functions
58 0x0: decode RS {
59 0x0: decode RT_RD {
60 0x0: decode SA default Nop::nop() {
61 0x1: ssnop({{;}});
62 0x3: ehb({{;}});
63 }
64 default: sll({{ Rd = Rt << SA; }});
65 }
66 }
67
68 0x2: decode RS_SRL {
69 0x0:decode SRL {
70 0: srl({{ Rd = Rt >> SA; }});
71
72 //Hardcoded assuming 32-bit ISA,
73 //probably need parameter here
74 1: rotr({{
75 Rd = (Rt << (32 - SA)) | (Rt >> SA);
76 }});
77 }
78 }
79
80 0x3: decode RS {
81 0x0: sra({{
82 uint32_t temp = Rt >> SA;
83 if ( (Rt & 0x80000000) > 0 ) {
84 uint32_t mask = 0x80000000;
85 for(int i=0; i < SA; i++) {
86 temp |= mask;
87 mask = mask >> 1;
88 }
89 }
90 Rd = temp;
91 }});
92 }
93
94 0x4: sllv({{ Rd = Rt << Rs<4:0>; }});
95
96 0x6: decode SRLV {
97 0: srlv({{ Rd = Rt >> Rs<4:0>; }});
98
99 //Hardcoded assuming 32-bit ISA,
100 //probably need parameter here
101 1: rotrv({{
102 Rd = (Rt << (32 - Rs<4:0>)) | (Rt >> Rs<4:0>);
103 }});
104 }
105
106 0x7: srav({{
107 int shift_amt = Rs<4:0>;
108
109 uint32_t temp = Rt >> shift_amt;
110
111 if ((Rt & 0x80000000) > 0) {
112 uint32_t mask = 0x80000000;
113 for (int i = 0; i < shift_amt; i++) {
114 temp |= mask;
115 mask = mask >> 1;
116 }
117 }
118 Rd = temp;
119 }});
120 }
121 }
122
123 0x1: decode FUNCTION_LO {
124 //Table A-3 Note: "Specific encodings of the hint field are
125 //used to distinguish JR from JR.HB and JALR from JALR.HB"
126 format Jump {
127 0x0: decode HINT {
128 0x1: jr_hb({{
129 Config1Reg config1 = Config1;
130 if (config1.ca == 0) {
131 NNPC = Rs;
132 } else {
133 panic("MIPS16e not supported\n");
134 }
135 }}, IsReturn, ClearHazards);
136 default: jr({{
137 Config1Reg config1 = Config1;
138 if (config1.ca == 0) {
139 NNPC = Rs;
140 } else {
141 panic("MIPS16e not supported\n");
142 }
143 }}, IsReturn);
144 }
145
146 0x1: decode HINT {
147 0x1: jalr_hb({{
148 Rd = NNPC;
149 NNPC = Rs;
150 }}, IsCall, ClearHazards);
151 default: jalr({{
152 Rd = NNPC;
153 NNPC = Rs;
154 }}, IsCall);
155 }
156 }
157
158 format BasicOp {
159 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
160 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
161 0x4: decode FullSystemInt {
162 0: syscall_se({{
163 fault = std::make_shared<SESyscallFault>();
164 }});
165 default: syscall({{
166 fault = std::make_shared<SystemCallFault>();
167 }});
168 }
169 0x7: sync({{ ; }}, IsMemBarrier);
170 0x5: break({{fault = std::make_shared<BreakpointFault>();}});
171 }
172
173 }
174
175 0x2: decode FUNCTION_LO {
176 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }},
177 IntMultOp, IsIprAccess);
178 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
179 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }},
180 IntMultOp, IsIprAccess);
181 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
182 }
183
184 0x3: decode FUNCTION_LO {
185 format HiLoRdSelValOp {
186 0x0: mult({{ val = Rs_sd * Rt_sd; }}, IntMultOp);
187 0x1: multu({{ val = Rs_ud * Rt_ud; }}, IntMultOp);
188 }
189
190 format HiLoOp {
191 0x2: div({{
192 if (Rt_sd != 0) {
193 HI0 = Rs_sd % Rt_sd;
194 LO0 = Rs_sd / Rt_sd;
195 }
196 }}, IntDivOp);
197
198 0x3: divu({{
199 if (Rt_ud != 0) {
200 HI0 = Rs_ud % Rt_ud;
201 LO0 = Rs_ud / Rt_ud;
202 }
203 }}, IntDivOp);
204 }
205 }
206
207 0x4: decode HINT {
208 0x0: decode FUNCTION_LO {
209 format IntOp {
210 0x0: add({{
211 uint32_t result;
212 Rd = result = Rs + Rt;
213 if (FullSystem &&
214 findOverflow(32, result, Rs, Rt)) {
215 fault = std::make_shared<IntegerOverflowFault>();
216 }
217 }});
218 0x1: addu({{ Rd = Rs_sw + Rt_sw;}});
219 0x2: sub({{
220 uint32_t result;
221 Rd = result = Rs - Rt;
222 if (FullSystem &&
223 findOverflow(32, result, Rs, ~Rt)) {
224 fault = std::make_shared<IntegerOverflowFault>();
225 }
226 }});
227 0x3: subu({{ Rd = Rs_sw - Rt_sw; }});
228 0x4: and({{ Rd = Rs & Rt; }});
229 0x5: or({{ Rd = Rs | Rt; }});
230 0x6: xor({{ Rd = Rs ^ Rt; }});
231 0x7: nor({{ Rd = ~(Rs | Rt); }});
232 }
233 }
234 }
235
236 0x5: decode HINT {
237 0x0: decode FUNCTION_LO {
238 format IntOp{
239 0x2: slt({{ Rd = (Rs_sw < Rt_sw) ? 1 : 0 }});
240 0x3: sltu({{ Rd = (Rs < Rt) ? 1 : 0 }});
241 }
242 }
243 }
244
245 0x6: decode FUNCTION_LO {
246 format Trap {
247 0x0: tge({{ cond = (Rs_sw >= Rt_sw); }});
248 0x1: tgeu({{ cond = (Rs >= Rt); }});
249 0x2: tlt({{ cond = (Rs_sw < Rt_sw); }});
250 0x3: tltu({{ cond = (Rs < Rt); }});
251 0x4: teq({{ cond = (Rs_sw == Rt_sw); }});
252 0x6: tne({{ cond = (Rs_sw != Rt_sw); }});
253 }
254 }
255 }
256
257 0x1: decode REGIMM_HI {
258 0x0: decode REGIMM_LO {
259 format Branch {
260 0x0: bltz({{ cond = (Rs_sw < 0); }});
261 0x1: bgez({{ cond = (Rs_sw >= 0); }});
262 0x2: bltzl({{ cond = (Rs_sw < 0); }}, Likely);
263 0x3: bgezl({{ cond = (Rs_sw >= 0); }}, Likely);
264 }
265 }
266
267 0x1: decode REGIMM_LO {
268 format TrapImm {
269 0x0: tgei( {{ cond = (Rs_sw >= (int16_t)INTIMM); }});
270 0x1: tgeiu({{
271 cond = (Rs >= (uint32_t)(int32_t)(int16_t)INTIMM);
272 }});
273 0x2: tlti( {{ cond = (Rs_sw < (int16_t)INTIMM); }});
274 0x3: tltiu({{
275 cond = (Rs < (uint32_t)(int32_t)(int16_t)INTIMM);
276 }});
277 0x4: teqi( {{ cond = (Rs_sw == (int16_t)INTIMM); }});
278 0x6: tnei( {{ cond = (Rs_sw != (int16_t)INTIMM); }});
279 }
280 }
281
282 0x2: decode REGIMM_LO {
283 format Branch {
284 0x0: bltzal({{ cond = (Rs_sw < 0); }}, Link);
285 0x1: decode RS {
286 0x0: bal ({{ cond = 1; }}, IsCall, Link);
287 default: bgezal({{ cond = (Rs_sw >= 0); }}, Link);
288 }
289 0x2: bltzall({{ cond = (Rs_sw < 0); }}, Link, Likely);
290 0x3: bgezall({{ cond = (Rs_sw >= 0); }}, Link, Likely);
291 }
292 }
293
294 0x3: decode REGIMM_LO {
295 // from Table 5-4 MIPS32 REGIMM Encoding of rt Field
296 // (DSP ASE MANUAL)
297 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }});
298 format WarnUnimpl {
299 0x7: synci();
300 }
301 }
302 }
303
304 format Jump {
305 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }});
306 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},
307 IsCall, Link);
308 }
309
310 format Branch {
311 0x4: decode RS_RT {
312 0x0: b({{ cond = 1; }});
313 default: beq({{ cond = (Rs_sw == Rt_sw); }});
314 }
315 0x5: bne({{ cond = (Rs_sw != Rt_sw); }});
316 0x6: blez({{ cond = (Rs_sw <= 0); }});
317 0x7: bgtz({{ cond = (Rs_sw > 0); }});
318 }
319 }
320
321 0x1: decode OPCODE_LO {
322 format IntImmOp {
323 0x0: addi({{
324 uint32_t result;
325 Rt = result = Rs + imm;
326 if (FullSystem &&
327 findOverflow(32, result, Rs, imm)) {
328 fault = std::make_shared<IntegerOverflowFault>();
329 }
330 }});
331 0x1: addiu({{ Rt = Rs_sw + imm; }});
332 0x2: slti({{ Rt = (Rs_sw < imm) ? 1 : 0 }});
333 0x3: sltiu({{ Rt = (Rs < (uint32_t)sextImm) ? 1 : 0;}});
334 0x4: andi({{ Rt = Rs_sw & zextImm; }});
335 0x5: ori({{ Rt = Rs_sw | zextImm; }});
336 0x6: xori({{ Rt = Rs_sw ^ zextImm; }});
337
338 0x7: decode RS {
339 0x0: lui({{ Rt = imm << 16; }});
340 }
341 }
342 }
343
344 0x2: decode OPCODE_LO {
345 //Table A-11 MIPS32 COP0 Encoding of rs Field
346 0x0: decode RS_MSB {
347 0x0: decode RS {
348 format CP0Control {
349 0x0: mfc0({{
350 Config3Reg config3 = Config3;
351 PageGrainReg pageGrain = PageGrain;
352 Rt = CP0_RD_SEL;
353 /* Hack for PageMask */
354 if (RD == 5) {
355 // PageMask
356 if (config3.sp == 0 || pageGrain.esp == 0)
357 Rt &= 0xFFFFE7FF;
358 }
359 }});
360 0x4: mtc0({{
361 CP0_RD_SEL = Rt;
362 CauseReg cause = Cause;
363 IntCtlReg intCtl = IntCtl;
364 if (RD == 11) {
365 // Compare
366 if (cause.ti == 1) {
367 cause.ti = 0;
368 int offset = 10; // corresponding to cause.ip0
369 offset += intCtl.ipti - 2;
370 replaceBits(cause, offset, offset, 0);
371 }
372 }
373 Cause = cause;
374 }});
375 }
376 format CP0Unimpl {
377 0x1: dmfc0();
378 0x5: dmtc0();
379 default: unknown();
380 }
381 format MT_MFTR {
382 // Decode MIPS MT MFTR instruction into sub-instructions
383 0x8: decode MT_U {
384 0x0: mftc0({{
385 data = readRegOtherThread(xc, RegId(MiscRegClass,
386 (RT << 3 | SEL)));
387 }});
388 0x1: decode SEL {
389 0x0: mftgpr({{
390 data = readRegOtherThread(xc,
391 RegId(IntRegClass, RT));
392 }});
393 0x1: decode RT {
394 0x0: mftlo_dsp0({{
395 data = readRegOtherThread(xc,
396 RegId(IntRegClass, INTREG_DSP_LO0));
397 }});
398 0x1: mfthi_dsp0({{
399 data = readRegOtherThread(xc,
400 RegId(IntRegClass, INTREG_DSP_HI0));
401 }});
402 0x2: mftacx_dsp0({{
403 data = readRegOtherThread(xc,
404 RegId(IntRegClass, INTREG_DSP_ACX0));
405 }});
406 0x4: mftlo_dsp1({{
407 data = readRegOtherThread(xc,
408 RegId(IntRegClass, INTREG_DSP_LO1));
409 }});
410 0x5: mfthi_dsp1({{
411 data = readRegOtherThread(xc,
412 RegId(IntRegClass, INTREG_DSP_HI1));
413 }});
414 0x6: mftacx_dsp1({{
415 data = readRegOtherThread(xc,
416 RegId(IntRegClass, INTREG_DSP_ACX1));
417 }});
418 0x8: mftlo_dsp2({{
419 data = readRegOtherThread(xc,
420 RegId(IntRegClass, INTREG_DSP_LO2));
421 }});
422 0x9: mfthi_dsp2({{
423 data = readRegOtherThread(xc,
424 RegId(IntRegClass, INTREG_DSP_HI2));
425 }});
426 0x10: mftacx_dsp2({{
427 data = readRegOtherThread(xc,
428 RegId(IntRegClass, INTREG_DSP_ACX2));
429 }});
430 0x12: mftlo_dsp3({{
431 data = readRegOtherThread(xc,
432 RegId(IntRegClass, INTREG_DSP_LO3));
433 }});
434 0x13: mfthi_dsp3({{
435 data = readRegOtherThread(xc,
436 RegId(IntRegClass, INTREG_DSP_HI3));
437 }});
438 0x14: mftacx_dsp3({{
439 data = readRegOtherThread(xc,
440 RegId(IntRegClass, INTREG_DSP_ACX3));
441 }});
442 0x16: mftdsp({{
443 data = readRegOtherThread(xc,
444 RegId(IntRegClass, INTREG_DSP_CONTROL));
445 }});
446 default: CP0Unimpl::unknown();
447 }
448 0x2: decode MT_H {
449 0x0: mftc1({{
450 data = readRegOtherThread(xc,
451 RegId(FloatRegClass, RT));
452 }});
453 0x1: mfthc1({{
454 data = readRegOtherThread(xc,
455 RegId(FloatRegClass, RT));
456 }});
457 }
458 0x3: cftc1({{
459 uint32_t fcsr_val = readRegOtherThread(xc,
460 RegId(FloatRegClass, FLOATREG_FCSR));
461 switch (RT) {
462 case 0:
463 data = readRegOtherThread(xc,
464 RegId(MiscRegClass, FLOATREG_FIR));
465 break;
466 case 25:
467 data = (fcsr_val & 0xFE000000 >> 24) |
468 (fcsr_val & 0x00800000 >> 23);
469 break;
470 case 26:
471 data = fcsr_val & 0x0003F07C;
472 break;
473 case 28:
474 data = (fcsr_val & 0x00000F80) |
475 (fcsr_val & 0x01000000 >> 21) |
476 (fcsr_val & 0x00000003);
477 break;
478 case 31:
479 data = fcsr_val;
480 break;
481 default:
482 fatal("FP Control Value (%d) Not Valid");
483 }
484 }});
485 default: CP0Unimpl::unknown();
486 }
487 }
488 }
489
490 format MT_MTTR {
491 // Decode MIPS MT MTTR instruction into sub-instructions
492 0xC: decode MT_U {
493 0x0: mttc0({{ setRegOtherThread(xc,
494 RegId(MiscRegClass, (RD << 3 | SEL)), Rt);
495 }});
496 0x1: decode SEL {
497 0x0: mttgpr({{ setRegOtherThread(xc,
498 RegId(IntRegClass, RD), Rt);
499 }});
500 0x1: decode RT {
501 0x0: mttlo_dsp0({{ setRegOtherThread(xc,
502 RegId(IntRegClass, INTREG_DSP_LO0), Rt);
503 }});
504 0x1: mtthi_dsp0({{ setRegOtherThread(xc,
505 RegId(IntRegClass, INTREG_DSP_HI0), Rt);
506 }});
507 0x2: mttacx_dsp0({{ setRegOtherThread(xc,
508 RegId(IntRegClass, INTREG_DSP_ACX0), Rt);
509 }});
510 0x4: mttlo_dsp1({{ setRegOtherThread(xc,
511 RegId(IntRegClass, INTREG_DSP_LO1), Rt);
512 }});
513 0x5: mtthi_dsp1({{ setRegOtherThread(xc,
514 RegId(IntRegClass, INTREG_DSP_HI1), Rt);
515 }});
516 0x6: mttacx_dsp1({{ setRegOtherThread(xc,
517 RegId(IntRegClass, INTREG_DSP_ACX1), Rt);
518 }});
519 0x8: mttlo_dsp2({{ setRegOtherThread(xc,
520 RegId(IntRegClass, INTREG_DSP_LO2), Rt);
521 }});
522 0x9: mtthi_dsp2({{ setRegOtherThread(xc,
523 RegId(IntRegClass, INTREG_DSP_HI2), Rt);
524 }});
525 0x10: mttacx_dsp2({{ setRegOtherThread(xc,
526 RegId(IntRegClass, INTREG_DSP_ACX2), Rt);
527 }});
528 0x12: mttlo_dsp3({{ setRegOtherThread(xc,
529 RegId(IntRegClass, INTREG_DSP_LO3), Rt);
530 }});
531 0x13: mtthi_dsp3({{ setRegOtherThread(xc,
532 RegId(IntRegClass, INTREG_DSP_HI3), Rt);
533 }});
534 0x14: mttacx_dsp3({{ setRegOtherThread(xc,
535 RegId(IntRegClass, INTREG_DSP_ACX3), Rt);
536 }});
537 0x16: mttdsp({{ setRegOtherThread(xc,
538 RegId(IntRegClass, INTREG_DSP_CONTROL), Rt);
539 }});
540 default: CP0Unimpl::unknown();
541
542 }
543 0x2: mttc1({{
544 uint64_t data = readRegOtherThread(xc,
545 RegId(FloatRegClass, RD));
546 data = insertBits(data, MT_H ? 63 : 31,
547 MT_H ? 32 : 0, Rt);
548 setRegOtherThread(xc, RegId(FloatRegClass, RD),
549 data);
550 }});
551 0x3: cttc1({{
552 uint32_t data;
553 switch (RD) {
554 case 25:
555 data = (Rt<7:1> << 25) | // move 31-25
556 (FCSR & 0x01000000) | // bit 24
557 (FCSR & 0x004FFFFF); // bit 22-0
558 break;
559 case 26:
560 data = (FCSR & 0xFFFC0000) | // move 31-18
561 Rt<17:12> << 12 | // bit 17-12
562 // bit 11-7
563 (FCSR & 0x00000F80) << 7 |
564 Rt<6:2> << 2 | // bit 6-2
565 (FCSR & 0x00000002); // bit 1...0
566 break;
567 case 28:
568 data = (FCSR & 0xFE000000) | // move 31-25
569 Rt<2:2> << 24 | // bit 24
570 // bit 23-12
571 (FCSR & 0x00FFF000) << 23 |
572 Rt<11:7> << 7 | // bit 24
573 (FCSR & 0x000007E) |
574 Rt<1:0>; // bit 22-0
575 break;
576 case 31:
577 data = Rt;
578 break;
579 default:
580 panic("FP Control Value (%d) "
581 "Not Available. Ignoring "
582 "Access to Floating Control "
583 "S""tatus Register", FS);
584 }
585 setRegOtherThread(xc,
586 RegId(FloatRegClass, FLOATREG_FCSR), data);
587 }});
588 default: CP0Unimpl::unknown();
589 }
590 }
591 }
592 0xB: decode RD {
593 format MT_Control {
594 0x0: decode POS {
595 0x0: decode SEL {
596 0x1: decode SC {
597 0x0: dvpe({{
598 MVPControlReg mvpControl = MVPControl;
599 VPEConf0Reg vpeConf0 = VPEConf0;
600 Rt = MVPControl;
601 if (vpeConf0.mvp == 1)
602 mvpControl.evp = 0;
603 MVPControl = mvpControl;
604 }});
605 0x1: evpe({{
606 MVPControlReg mvpControl = MVPControl;
607 VPEConf0Reg vpeConf0 = VPEConf0;
608 Rt = MVPControl;
609 if (vpeConf0.mvp == 1)
610 mvpControl.evp = 1;
611 MVPControl = mvpControl;
612 }});
613 default:CP0Unimpl::unknown();
614 }
615 default:CP0Unimpl::unknown();
616 }
617 default:CP0Unimpl::unknown();
618 }
619 0x1: decode POS {
620 0xF: decode SEL {
621 0x1: decode SC {
622 0x0: dmt({{
623 VPEControlReg vpeControl = VPEControl;
624 Rt = vpeControl;
625 vpeControl.te = 0;
626 VPEControl = vpeControl;
627 }});
628 0x1: emt({{
629 VPEControlReg vpeControl = VPEControl;
630 Rt = vpeControl;
631 vpeControl.te = 1;
632 VPEControl = vpeControl;
633 }});
634 default:CP0Unimpl::unknown();
635 }
636 default:CP0Unimpl::unknown();
637 }
638 default:CP0Unimpl::unknown();
639 }
640 }
641 0xC: decode POS {
642 0x0: decode SC {
643 0x0: CP0Control::di({{
644 StatusReg status = Status;
645 ConfigReg config = Config;
646 // Rev 2.0 or beyond?
647 if (config.ar >= 1) {
648 Rt = status;
649 status.ie = 0;
650 } else {
651 // Enable this else branch once we
652 // actually set values for Config on init
653 fault = std::make_shared<ReservedInstructionFault>();
654 }
655 Status = status;
656 }});
657 0x1: CP0Control::ei({{
658 StatusReg status = Status;
659 ConfigReg config = Config;
660 if (config.ar >= 1) {
661 Rt = status;
662 status.ie = 1;
663 } else {
664 fault = std::make_shared<ReservedInstructionFault>();
665 }
666 }});
667 default:CP0Unimpl::unknown();
668 }
669 }
670 default: CP0Unimpl::unknown();
671 }
672 format CP0Control {
673 0xA: rdpgpr({{
674 ConfigReg config = Config;
675 if (config.ar >= 1) {
676 // Rev 2 of the architecture
677 panic("Shadow Sets Not Fully Implemented.\n");
678 } else {
679 fault = std::make_shared<ReservedInstructionFault>();
680 }
681 }});
682 0xE: wrpgpr({{
683 ConfigReg config = Config;
684 if (config.ar >= 1) {
685 // Rev 2 of the architecture
686 panic("Shadow Sets Not Fully Implemented.\n");
687 } else {
688 fault = std::make_shared<ReservedInstructionFault>();
689 }
690 }});
691 }
692 }
693
694 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
695 0x1: decode FUNCTION {
696 format CP0Control {
697 0x18: eret({{
698 StatusReg status = Status;
699 ConfigReg config = Config;
700 SRSCtlReg srsCtl = SRSCtl;
701 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
702 if (status.erl == 1) {
703 status.erl = 0;
704 NPC = ErrorEPC;
705 // Need to adjust NNPC, otherwise things break
706 NNPC = ErrorEPC + sizeof(MachInst);
707 } else {
708 NPC = EPC;
709 // Need to adjust NNPC, otherwise things break
710 NNPC = EPC + sizeof(MachInst);
711 status.exl = 0;
712 if (config.ar >=1 &&
713 srsCtl.hss > 0 &&
714 status.bev == 0) {
715 srsCtl.css = srsCtl.pss;
716 //xc->setShadowSet(srsCtl.pss);
717 }
718 }
719 LLFlag = 0;
720 Status = status;
721 SRSCtl = srsCtl;
722 }}, IsReturn, IsSerializing);
723
724 0x1F: deret({{
725 DebugReg debug = Debug;
726 if (debug.dm == 1) {
727 debug.dm = 1;
728 debug.iexi = 0;
729 NPC = DEPC;
730 } else {
731 NPC = NPC;
732 // Undefined;
733 }
734 Debug = debug;
735 }}, IsReturn, IsSerializing);
736 }
737 format CP0TLB {
738 0x01: tlbr({{
739 MipsISA::PTE *PTEntry =
740 dynamic_cast<MipsISA::TLB *>(
741 xc->tcBase()->getITBPtr())->
742 getEntry(Index & 0x7FFFFFFF);
743 if (PTEntry == NULL) {
744 fatal("Invalid PTE Entry received on "
745 "a TLBR instruction\n");
746 }
747 /* Setup PageMask */
748 // If 1KB pages are not enabled, a read of PageMask
749 // must return 0b00 in bits 12, 11
750 PageMask = (PTEntry->Mask << 11);
751 /* Setup EntryHi */
752 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid));
753 /* Setup Entry Lo0 */
754 EntryLo0 = ((PTEntry->PFN0 << 6) |
755 (PTEntry->C0 << 3) |
756 (PTEntry->D0 << 2) |
757 (PTEntry->V0 << 1) |
758 PTEntry->G);
759 /* Setup Entry Lo1 */
760 EntryLo1 = ((PTEntry->PFN1 << 6) |
761 (PTEntry->C1 << 3) |
762 (PTEntry->D1 << 2) |
763 (PTEntry->V1 << 1) |
764 PTEntry->G);
765 }}); // Need to hook up to TLB
766
767 0x02: tlbwi({{
768 //Create PTE
769 MipsISA::PTE newEntry;
770 //Write PTE
771 newEntry.Mask = (Addr)(PageMask >> 11);
772 newEntry.VPN = (Addr)(EntryHi >> 11);
773 /* PageGrain _ ESP Config3 _ SP */
774 if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) {
775 // If 1KB pages are *NOT* enabled, lowest bits of
776 // the mask are 0b11 for TLB writes
777 newEntry.Mask |= 0x3;
778 // Reset bits 0 and 1 if 1KB pages are not enabled
779 newEntry.VPN &= 0xFFFFFFFC;
780 }
781 newEntry.asid = (uint8_t)(EntryHi & 0xFF);
782
783 newEntry.PFN0 = (Addr)(EntryLo0 >> 6);
784 newEntry.PFN1 = (Addr)(EntryLo1 >> 6);
785 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
786 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
787 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
788 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
789 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
790 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
791 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
792 /* Now, compute the AddrShiftAmount and OffsetMask -
793 TLB optimizations */
794 /* Addr Shift Amount for 1KB or larger pages */
795 if ((newEntry.Mask & 0xFFFF) == 3) {
796 newEntry.AddrShiftAmount = 12;
797 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) {
798 newEntry.AddrShiftAmount = 10;
799 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) {
800 newEntry.AddrShiftAmount = 14;
801 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) {
802 newEntry.AddrShiftAmount = 16;
803 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) {
804 newEntry.AddrShiftAmount = 18;
805 } else if ((newEntry.Mask & 0xFF00) == 0x0300) {
806 newEntry.AddrShiftAmount = 20;
807 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) {
808 newEntry.AddrShiftAmount = 22;
809 } else if ((newEntry.Mask & 0xF000) == 0x3000) {
810 newEntry.AddrShiftAmount = 24;
811 } else if ((newEntry.Mask & 0xC000) == 0xC000) {
812 newEntry.AddrShiftAmount = 26;
813 } else if ((newEntry.Mask & 0x30000) == 0x30000) {
814 newEntry.AddrShiftAmount = 28;
815 } else {
816 fatal("Invalid Mask Pattern Detected!\n");
817 }
818 newEntry.OffsetMask =
819 (1 << newEntry.AddrShiftAmount) - 1;
820
821 auto ptr = dynamic_cast<MipsISA::TLB *>(
822 xc->tcBase()->getITBPtr());
823 Config3Reg config3 = Config3;
824 PageGrainReg pageGrain = PageGrain;
825 int SP = 0;
826 if (bits(config3, config3.sp) == 1 &&
827 bits(pageGrain, pageGrain.esp) == 1) {
828 SP = 1;
829 }
830 ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP);
831 }});
832 0x06: tlbwr({{
833 //Create PTE
834 MipsISA::PTE newEntry;
835 //Write PTE
836 newEntry.Mask = (Addr)(PageMask >> 11);
837 newEntry.VPN = (Addr)(EntryHi >> 11);
838 /* PageGrain _ ESP Config3 _ SP */
839 if (bits(PageGrain, 28) == 0 ||
840 bits(Config3, 4) == 0) {
841 // If 1KB pages are *NOT* enabled, lowest bits of
842 // the mask are 0b11 for TLB writes
843 newEntry.Mask |= 0x3;
844 // Reset bits 0 and 1 if 1KB pages are not enabled
845 newEntry.VPN &= 0xFFFFFFFC;
846 }
847 newEntry.asid = (uint8_t)(EntryHi & 0xFF);
848
849 newEntry.PFN0 = (Addr)(EntryLo0 >> 6);
850 newEntry.PFN1 = (Addr)(EntryLo1 >> 6);
851 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
852 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
853 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
854 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
855 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
856 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
857 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
858 /* Now, compute the AddrShiftAmount and OffsetMask -
859 TLB optimizations */
860 /* Addr Shift Amount for 1KB or larger pages */
861 if ((newEntry.Mask & 0xFFFF) == 3){
862 newEntry.AddrShiftAmount = 12;
863 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) {
864 newEntry.AddrShiftAmount = 10;
865 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) {
866 newEntry.AddrShiftAmount = 14;
867 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) {
868 newEntry.AddrShiftAmount = 16;
869 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) {
870 newEntry.AddrShiftAmount = 18;
871 } else if ((newEntry.Mask & 0xFF00) == 0x0300) {
872 newEntry.AddrShiftAmount = 20;
873 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) {
874 newEntry.AddrShiftAmount = 22;
875 } else if ((newEntry.Mask & 0xF000) == 0x3000) {
876 newEntry.AddrShiftAmount = 24;
877 } else if ((newEntry.Mask & 0xC000) == 0xC000) {
878 newEntry.AddrShiftAmount = 26;
879 } else if ((newEntry.Mask & 0x30000) == 0x30000) {
880 newEntry.AddrShiftAmount = 28;
881 } else {
882 fatal("Invalid Mask Pattern Detected!\n");
883 }
884 newEntry.OffsetMask =
885 (1 << newEntry.AddrShiftAmount) - 1;
886
887 auto ptr = dynamic_cast<MipsISA::TLB *>(
888 xc->tcBase()->getITBPtr());
889 Config3Reg config3 = Config3;
890 PageGrainReg pageGrain = PageGrain;
891 int SP = 0;
892 if (bits(config3, config3.sp) == 1 &&
893 bits(pageGrain, pageGrain.esp) == 1) {
894 SP = 1;
895 }
896 ptr->insertAt(newEntry, Random, SP);
897 }});
898
899 0x08: tlbp({{
900 Config3Reg config3 = Config3;
901 PageGrainReg pageGrain = PageGrain;
902 EntryHiReg entryHi = EntryHi;
903 int tlbIndex;
904 Addr vpn;
905 if (pageGrain.esp == 1 && config3.sp ==1) {
906 vpn = EntryHi >> 11;
907 } else {
908 // Mask off lower 2 bits
909 vpn = ((EntryHi >> 11) & 0xFFFFFFFC);
910 }
911 tlbIndex = dynamic_cast<MipsISA::TLB *>(
912 xc->tcBase()->getITBPtr())->
913 probeEntry(vpn, entryHi.asid);
914 // Check TLB for entry matching EntryHi
915 if (tlbIndex != -1) {
916 Index = tlbIndex;
917 } else {
918 // else, set Index = 1 << 31
919 Index = (1 << 31);
920 }
921 }});
922 }
923 format CP0Unimpl {
924 0x20: wait();
925 }
926 default: CP0Unimpl::unknown();
927 }
928 }
929
930 //Table A-13 MIPS32 COP1 Encoding of rs Field
931 0x1: decode RS_MSB {
932 0x0: decode RS_HI {
933 0x0: decode RS_LO {
934 format CP1Control {
935 0x0: mfc1 ({{ Rt = Fs_uw; }});
936
937 0x2: cfc1({{
938 switch (FS) {
939 case 0:
940 Rt = FIR;
941 break;
942 case 25:
943 Rt = (FCSR & 0xFE000000) >> 24 |
944 (FCSR & 0x00800000) >> 23;
945 break;
946 case 26:
947 Rt = (FCSR & 0x0003F07C);
948 break;
949 case 28:
950 Rt = (FCSR & 0x00000F80) |
951 (FCSR & 0x01000000) >> 21 |
952 (FCSR & 0x00000003);
953 break;
954 case 31:
955 Rt = FCSR;
956 break;
957 default:
958 warn("FP Control Value (%d) Not Valid");
959 }
960 }});
961
962 0x3: mfhc1({{ Rt = Fs_ud<63:32>; }});
963
964 0x4: mtc1({{ Fs_uw = Rt; }});
965
966 0x6: ctc1({{
967 switch (FS) {
968 case 25:
969 FCSR = (Rt<7:1> << 25) | // move 31-25
970 (FCSR & 0x01000000) | // bit 24
971 (FCSR & 0x004FFFFF); // bit 22-0
972 break;
973 case 26:
974 FCSR = (FCSR & 0xFFFC0000) | // move 31-18
975 Rt<17:12> << 12 | // bit 17-12
976 (FCSR & 0x00000F80) << 7 | // bit 11-7
977 Rt<6:2> << 2 | // bit 6-2
978 (FCSR & 0x00000002); // bit 1-0
979 break;
980 case 28:
981 FCSR = (FCSR & 0xFE000000) | // move 31-25
982 Rt<2:2> << 24 | // bit 24
983 (FCSR & 0x00FFF000) << 23 | // bit 23-12
984 Rt<11:7> << 7 | // bit 24
985 (FCSR & 0x000007E) |
986 Rt<1:0>; // bit 22-0
987 break;
988 case 31:
989 FCSR = Rt;
990 break;
991
992 default:
993 panic("FP Control Value (%d) "
994 "Not Available. Ignoring Access "
995 "to Floating Control Status "
996 "Register", FS);
997 }
998 }});
999
1000 0x7: mthc1({{
1001 uint64_t fs_hi = Rt;
1002 uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF;
1003 Fs_ud = (fs_hi << 32) | fs_lo;
1004 }});
1005
1006 }
1007 format CP1Unimpl {
1008 0x1: dmfc1();
1009 0x5: dmtc1();
1010 }
1011 }
1012
1013 0x1: decode RS_LO {
1014 0x0: decode ND {
1015 format Branch {
1016 0x0: decode TF {
1017 0x0: bc1f({{
1018 cond = getCondCode(FCSR, BRANCH_CC) == 0;
1019 }});
1020 0x1: bc1t({{
1021 cond = getCondCode(FCSR, BRANCH_CC) == 1;
1022 }});
1023 }
1024 0x1: decode TF {
1025 0x0: bc1fl({{
1026 cond = getCondCode(FCSR, BRANCH_CC) == 0;
1027 }}, Likely);
1028 0x1: bc1tl({{
1029 cond = getCondCode(FCSR, BRANCH_CC) == 1;
1030 }}, Likely);
1031 }
1032 }
1033 }
1034 format CP1Unimpl {
1035 0x1: bc1any2();
1036 0x2: bc1any4();
1037 default: unknown();
1038 }
1039 }
1040 }
1041
1042 0x1: decode RS_HI {
1043 0x2: decode RS_LO {
1044 //Table A-14 MIPS32 COP1 Encoding of Function Field When
1045 //rs=S (( single-precision floating point))
1046 0x0: decode FUNCTION_HI {
1047 0x0: decode FUNCTION_LO {
1048 format FloatOp {
1049 0x0: add_s({{ Fd_sf = Fs_sf + Ft_sf; }});
1050 0x1: sub_s({{ Fd_sf = Fs_sf - Ft_sf; }});
1051 0x2: mul_s({{ Fd_sf = Fs_sf * Ft_sf; }});
1052 0x3: div_s({{ Fd_sf = Fs_sf / Ft_sf; }});
1053 0x4: sqrt_s({{ Fd_sf = sqrt(Fs_sf); }});
1054 0x5: abs_s({{ Fd_sf = fabs(Fs_sf); }});
1055 0x7: neg_s({{ Fd_sf = -Fs_sf; }});
1056 }
1057 0x6: BasicOp::mov_s({{ Fd_sf = Fs_sf; }});
1058 }
1059 0x1: decode FUNCTION_LO {
1060 format FloatConvertOp {
1061 0x0: round_l_s({{ val = Fs_sf; }},
1062 ToLong, Round);
1063 0x1: trunc_l_s({{ val = Fs_sf; }},
1064 ToLong, Trunc);
1065 0x2: ceil_l_s({{ val = Fs_sf;}},
1066 ToLong, Ceil);
1067 0x3: floor_l_s({{ val = Fs_sf; }},
1068 ToLong, Floor);
1069 0x4: round_w_s({{ val = Fs_sf; }},
1070 ToWord, Round);
1071 0x5: trunc_w_s({{ val = Fs_sf; }},
1072 ToWord, Trunc);
1073 0x6: ceil_w_s({{ val = Fs_sf; }},
1074 ToWord, Ceil);
1075 0x7: floor_w_s({{ val = Fs_sf; }},
1076 ToWord, Floor);
1077 }
1078 }
1079
1080 0x2: decode FUNCTION_LO {
1081 0x1: decode MOVCF {
1082 format BasicOp {
1083 0x0: movf_s({{
1084 Fd = (getCondCode(FCSR,CC) == 0) ?
1085 Fs : Fd;
1086 }});
1087 0x1: movt_s({{
1088 Fd = (getCondCode(FCSR,CC) == 1) ?
1089 Fs : Fd;
1090 }});
1091 }
1092 }
1093
1094 format BasicOp {
1095 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
1096 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
1097 }
1098
1099 format FloatOp {
1100 0x5: recip_s({{ Fd = 1 / Fs; }});
1101 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }});
1102 }
1103 format CP1Unimpl {
1104 default: unknown();
1105 }
1106 }
1107 0x3: CP1Unimpl::unknown();
1108
1109 0x4: decode FUNCTION_LO {
1110 format FloatConvertOp {
1111 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble);
1112 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord);
1113 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong);
1114 }
1115
1116 0x6: FloatOp::cvt_ps_s({{
1117 Fd_ud = (uint64_t)Fs_uw << 32 |
1118 (uint64_t)Ft_uw;
1119 }});
1120 format CP1Unimpl {
1121 default: unknown();
1122 }
1123 }
1124 0x5: CP1Unimpl::unknown();
1125
1126 0x6: decode FUNCTION_LO {
1127 format FloatCompareOp {
1128 0x0: c_f_s({{ cond = 0; }},
1129 SinglePrecision, UnorderedFalse);
1130 0x1: c_un_s({{ cond = 0; }},
1131 SinglePrecision, UnorderedTrue);
1132 0x2: c_eq_s({{ cond = (Fs_sf == Ft_sf); }},
1133 UnorderedFalse);
1134 0x3: c_ueq_s({{ cond = (Fs_sf == Ft_sf); }},
1135 UnorderedTrue);
1136 0x4: c_olt_s({{ cond = (Fs_sf < Ft_sf); }},
1137 UnorderedFalse);
1138 0x5: c_ult_s({{ cond = (Fs_sf < Ft_sf); }},
1139 UnorderedTrue);
1140 0x6: c_ole_s({{ cond = (Fs_sf <= Ft_sf); }},
1141 UnorderedFalse);
1142 0x7: c_ule_s({{ cond = (Fs_sf <= Ft_sf); }},
1143 UnorderedTrue);
1144 }
1145 }
1146
1147 0x7: decode FUNCTION_LO {
1148 format FloatCompareOp {
1149 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision,
1150 UnorderedFalse, QnanException);
1151 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision,
1152 UnorderedTrue, QnanException);
1153 0x2: c_seq_s({{ cond = (Fs_sf == Ft_sf); }},
1154 UnorderedFalse, QnanException);
1155 0x3: c_ngl_s({{ cond = (Fs_sf == Ft_sf); }},
1156 UnorderedTrue, QnanException);
1157 0x4: c_lt_s({{ cond = (Fs_sf < Ft_sf); }},
1158 UnorderedFalse, QnanException);
1159 0x5: c_nge_s({{ cond = (Fs_sf < Ft_sf); }},
1160 UnorderedTrue, QnanException);
1161 0x6: c_le_s({{ cond = (Fs_sf <= Ft_sf); }},
1162 UnorderedFalse, QnanException);
1163 0x7: c_ngt_s({{ cond = (Fs_sf <= Ft_sf); }},
1164 UnorderedTrue, QnanException);
1165 }
1166 }
1167 }
1168
1169 //Table A-15 MIPS32 COP1 Encoding of Function Field When
1170 //rs=D
1171 0x1: decode FUNCTION_HI {
1172 0x0: decode FUNCTION_LO {
1173 format FloatOp {
1174 0x0: add_d({{ Fd_df = Fs_df + Ft_df; }});
1175 0x1: sub_d({{ Fd_df = Fs_df - Ft_df; }});
1176 0x2: mul_d({{ Fd_df = Fs_df * Ft_df; }});
1177 0x3: div_d({{ Fd_df = Fs_df / Ft_df; }});
1178 0x4: sqrt_d({{ Fd_df = sqrt(Fs_df); }});
1179 0x5: abs_d({{ Fd_df = fabs(Fs_df); }});
1180 0x7: neg_d({{ Fd_df = -1 * Fs_df; }});
1181 }
1182 0x6: BasicOp::mov_d({{ Fd_df = Fs_df; }});
1183 }
1184
1185 0x1: decode FUNCTION_LO {
1186 format FloatConvertOp {
1187 0x0: round_l_d({{ val = Fs_df; }},
1188 ToLong, Round);
1189 0x1: trunc_l_d({{ val = Fs_df; }},
1190 ToLong, Trunc);
1191 0x2: ceil_l_d({{ val = Fs_df; }},
1192 ToLong, Ceil);
1193 0x3: floor_l_d({{ val = Fs_df; }},
1194 ToLong, Floor);
1195 0x4: round_w_d({{ val = Fs_df; }},
1196 ToWord, Round);
1197 0x5: trunc_w_d({{ val = Fs_df; }},
1198 ToWord, Trunc);
1199 0x6: ceil_w_d({{ val = Fs_df; }},
1200 ToWord, Ceil);
1201 0x7: floor_w_d({{ val = Fs_df; }},
1202 ToWord, Floor);
1203 }
1204 }
1205
1206 0x2: decode FUNCTION_LO {
1207 0x1: decode MOVCF {
1208 format BasicOp {
1209 0x0: movf_d({{
1210 Fd_df = (getCondCode(FCSR,CC) == 0) ?
1211 Fs_df : Fd_df;
1212 }});
1213 0x1: movt_d({{
1214 Fd_df = (getCondCode(FCSR,CC) == 1) ?
1215 Fs_df : Fd_df;
1216 }});
1217 }
1218 }
1219
1220 format BasicOp {
1221 0x2: movz_d({{
1222 Fd_df = (Rt == 0) ? Fs_df : Fd_df;
1223 }});
1224 0x3: movn_d({{
1225 Fd_df = (Rt != 0) ? Fs_df : Fd_df;
1226 }});
1227 }
1228
1229 format FloatOp {
1230 0x5: recip_d({{ Fd_df = 1 / Fs_df; }});
1231 0x6: rsqrt_d({{ Fd_df = 1 / sqrt(Fs_df); }});
1232 }
1233 format CP1Unimpl {
1234 default: unknown();
1235 }
1236
1237 }
1238 0x4: decode FUNCTION_LO {
1239 format FloatConvertOp {
1240 0x0: cvt_s_d({{ val = Fs_df; }}, ToSingle);
1241 0x4: cvt_w_d({{ val = Fs_df; }}, ToWord);
1242 0x5: cvt_l_d({{ val = Fs_df; }}, ToLong);
1243 }
1244 default: CP1Unimpl::unknown();
1245 }
1246
1247 0x6: decode FUNCTION_LO {
1248 format FloatCompareOp {
1249 0x0: c_f_d({{ cond = 0; }},
1250 DoublePrecision, UnorderedFalse);
1251 0x1: c_un_d({{ cond = 0; }},
1252 DoublePrecision, UnorderedTrue);
1253 0x2: c_eq_d({{ cond = (Fs_df == Ft_df); }},
1254 UnorderedFalse);
1255 0x3: c_ueq_d({{ cond = (Fs_df == Ft_df); }},
1256 UnorderedTrue);
1257 0x4: c_olt_d({{ cond = (Fs_df < Ft_df); }},
1258 UnorderedFalse);
1259 0x5: c_ult_d({{ cond = (Fs_df < Ft_df); }},
1260 UnorderedTrue);
1261 0x6: c_ole_d({{ cond = (Fs_df <= Ft_df); }},
1262 UnorderedFalse);
1263 0x7: c_ule_d({{ cond = (Fs_df <= Ft_df); }},
1264 UnorderedTrue);
1265 }
1266 }
1267
1268 0x7: decode FUNCTION_LO {
1269 format FloatCompareOp {
1270 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision,
1271 UnorderedFalse, QnanException);
1272 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision,
1273 UnorderedTrue, QnanException);
1274 0x2: c_seq_d({{ cond = (Fs_df == Ft_df); }},
1275 UnorderedFalse, QnanException);
1276 0x3: c_ngl_d({{ cond = (Fs_df == Ft_df); }},
1277 UnorderedTrue, QnanException);
1278 0x4: c_lt_d({{ cond = (Fs_df < Ft_df); }},
1279 UnorderedFalse, QnanException);
1280 0x5: c_nge_d({{ cond = (Fs_df < Ft_df); }},
1281 UnorderedTrue, QnanException);
1282 0x6: c_le_d({{ cond = (Fs_df <= Ft_df); }},
1283 UnorderedFalse, QnanException);
1284 0x7: c_ngt_d({{ cond = (Fs_df <= Ft_df); }},
1285 UnorderedTrue, QnanException);
1286 }
1287 }
1288 default: CP1Unimpl::unknown();
1289 }
1290 0x2: CP1Unimpl::unknown();
1291 0x3: CP1Unimpl::unknown();
1292 0x7: CP1Unimpl::unknown();
1293
1294 //Table A-16 MIPS32 COP1 Encoding of Function
1295 //Field When rs=W
1296 0x4: decode FUNCTION {
1297 format FloatConvertOp {
1298 0x20: cvt_s_w({{ val = Fs_sw; }}, ToSingle);
1299 0x21: cvt_d_w({{ val = Fs_sw; }}, ToDouble);
1300 0x26: CP1Unimpl::cvt_ps_w();
1301 }
1302 default: CP1Unimpl::unknown();
1303 }
1304
1305 //Table A-16 MIPS32 COP1 Encoding of Function Field
1306 //When rs=L1
1307 //Note: "1. Format type L is legal only if 64-bit
1308 //floating point operations are enabled."
1309 0x5: decode FUNCTION {
1310 format FloatConvertOp {
1311 0x20: cvt_s_l({{ val = Fs_sd; }}, ToSingle);
1312 0x21: cvt_d_l({{ val = Fs_sd; }}, ToDouble);
1313 0x26: CP1Unimpl::cvt_ps_l();
1314 }
1315 default: CP1Unimpl::unknown();
1316 }
1317
1318 //Table A-17 MIPS64 COP1 Encoding of Function Field
1319 //When rs=PS1
1320 //Note: "1. Format type PS is legal only if 64-bit
1321 //floating point operations are enabled. "
1322 0x6: decode FUNCTION_HI {
1323 0x0: decode FUNCTION_LO {
1324 format Float64Op {
1325 0x0: add_ps({{
1326 Fd1_sf = Fs1_sf + Ft2_sf;
1327 Fd2_sf = Fs2_sf + Ft2_sf;
1328 }});
1329 0x1: sub_ps({{
1330 Fd1_sf = Fs1_sf - Ft2_sf;
1331 Fd2_sf = Fs2_sf - Ft2_sf;
1332 }});
1333 0x2: mul_ps({{
1334 Fd1_sf = Fs1_sf * Ft2_sf;
1335 Fd2_sf = Fs2_sf * Ft2_sf;
1336 }});
1337 0x5: abs_ps({{
1338 Fd1_sf = fabs(Fs1_sf);
1339 Fd2_sf = fabs(Fs2_sf);
1340 }});
1341 0x6: mov_ps({{
1342 Fd1_sf = Fs1_sf;
1343 Fd2_sf = Fs2_sf;
1344 }});
1345 0x7: neg_ps({{
1346 Fd1_sf = -(Fs1_sf);
1347 Fd2_sf = -(Fs2_sf);
1348 }});
1349 default: CP1Unimpl::unknown();
1350 }
1351 }
1352 0x1: CP1Unimpl::unknown();
1353 0x2: decode FUNCTION_LO {
1354 0x1: decode MOVCF {
1355 format Float64Op {
1356 0x0: movf_ps({{
1357 Fd1 = (getCondCode(FCSR, CC) == 0) ?
1358 Fs1 : Fd1;
1359 Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
1360 Fs2 : Fd2;
1361 }});
1362 0x1: movt_ps({{
1363 Fd2 = (getCondCode(FCSR, CC) == 1) ?
1364 Fs1 : Fd1;
1365 Fd2 = (getCondCode(FCSR, CC+1) == 1) ?
1366 Fs2 : Fd2;
1367 }});
1368 }
1369 }
1370
1371 format Float64Op {
1372 0x2: movz_ps({{
1373 Fd1 = (getCondCode(FCSR, CC) == 0) ?
1374 Fs1 : Fd1;
1375 Fd2 = (getCondCode(FCSR, CC) == 0) ?
1376 Fs2 : Fd2;
1377 }});
1378 0x3: movn_ps({{
1379 Fd1 = (getCondCode(FCSR, CC) == 1) ?
1380 Fs1 : Fd1;
1381 Fd2 = (getCondCode(FCSR, CC) == 1) ?
1382 Fs2 : Fd2;
1383 }});
1384 }
1385 default: CP1Unimpl::unknown();
1386 }
1387 0x3: CP1Unimpl::unknown();
1388 0x4: decode FUNCTION_LO {
1389 0x0: FloatOp::cvt_s_pu({{ Fd_sf = Fs2_sf; }});
1390 default: CP1Unimpl::unknown();
1391 }
1392
1393 0x5: decode FUNCTION_LO {
1394 0x0: FloatOp::cvt_s_pl({{ Fd_sf = Fs1_sf; }});
1395 format Float64Op {
1396 0x4: pll({{
1397 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft1_uw;
1398 }});
1399 0x5: plu({{
1400 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft2_uw;
1401 }});
1402 0x6: pul({{
1403 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft1_uw;
1404 }});
1405 0x7: puu({{
1406 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft2_uw;
1407 }});
1408 }
1409 default: CP1Unimpl::unknown();
1410 }
1411
1412 0x6: decode FUNCTION_LO {
1413 format FloatPSCompareOp {
1414 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1415 UnorderedFalse);
1416 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1417 UnorderedTrue);
1418 0x2: c_eq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }},
1419 {{ cond2 = (Fs2_sf == Ft2_sf); }},
1420 UnorderedFalse);
1421 0x3: c_ueq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }},
1422 {{ cond2 = (Fs2_sf == Ft2_sf); }},
1423 UnorderedTrue);
1424 0x4: c_olt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }},
1425 {{ cond2 = (Fs2_sf < Ft2_sf); }},
1426 UnorderedFalse);
1427 0x5: c_ult_ps({{ cond1 = (Fs_sf < Ft_sf); }},
1428 {{ cond2 = (Fs2_sf < Ft2_sf); }},
1429 UnorderedTrue);
1430 0x6: c_ole_ps({{ cond1 = (Fs_sf <= Ft_sf); }},
1431 {{ cond2 = (Fs2_sf <= Ft2_sf); }},
1432 UnorderedFalse);
1433 0x7: c_ule_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }},
1434 {{ cond2 = (Fs2_sf <= Ft2_sf); }},
1435 UnorderedTrue);
1436 }
1437 }
1438
1439 0x7: decode FUNCTION_LO {
1440 format FloatPSCompareOp {
1441 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1442 UnorderedFalse, QnanException);
1443 0x1: c_ngle_ps({{ cond1 = 0; }},
1444 {{ cond2 = 0; }},
1445 UnorderedTrue, QnanException);
1446 0x2: c_seq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }},
1447 {{ cond2 = (Fs2_sf == Ft2_sf); }},
1448 UnorderedFalse, QnanException);
1449 0x3: c_ngl_ps({{ cond1 = (Fs1_sf == Ft1_sf); }},
1450 {{ cond2 = (Fs2_sf == Ft2_sf); }},
1451 UnorderedTrue, QnanException);
1452 0x4: c_lt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }},
1453 {{ cond2 = (Fs2_sf < Ft2_sf); }},
1454 UnorderedFalse, QnanException);
1455 0x5: c_nge_ps({{ cond1 = (Fs1_sf < Ft1_sf); }},
1456 {{ cond2 = (Fs2_sf < Ft2_sf); }},
1457 UnorderedTrue, QnanException);
1458 0x6: c_le_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }},
1459 {{ cond2 = (Fs2_sf <= Ft2_sf); }},
1460 UnorderedFalse, QnanException);
1461 0x7: c_ngt_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }},
1462 {{ cond2 = (Fs2_sf <= Ft2_sf); }},
1463 UnorderedTrue, QnanException);
1464 }
1465 }
1466 }
1467 }
1468 default: CP1Unimpl::unknown();
1469 }
1470 }
1471
1472 //Table A-19 MIPS32 COP2 Encoding of rs Field
1473 0x2: decode RS_MSB {
1474 format CP2Unimpl {
1475 0x0: decode RS_HI {
1476 0x0: decode RS_LO {
1477 0x0: mfc2();
1478 0x2: cfc2();
1479 0x3: mfhc2();
1480 0x4: mtc2();
1481 0x6: ctc2();
1482 0x7: mftc2();
1483 default: unknown();
1484 }
1485
1486 0x1: decode ND {
1487 0x0: decode TF {
1488 0x0: bc2f();
1489 0x1: bc2t();
1490 default: unknown();
1491 }
1492
1493 0x1: decode TF {
1494 0x0: bc2fl();
1495 0x1: bc2tl();
1496 default: unknown();
1497 }
1498 default: unknown();
1499
1500 }
1501 default: unknown();
1502 }
1503 default: unknown();
1504 }
1505 }
1506
1507 //Table A-20 MIPS64 COP1X Encoding of Function Field 1
1508 //Note: "COP1X instructions are legal only if 64-bit floating point
1509 //operations are enabled."
1510 0x3: decode FUNCTION_HI {
1511 0x0: decode FUNCTION_LO {
1512 format LoadIndexedMemory {
1513 0x0: lwxc1({{ Fd_uw = Mem; }});
1514 0x1: ldxc1({{ Fd_ud = Mem_ud; }});
1515 0x5: luxc1({{ Fd_ud = Mem_ud; }},
1516 {{ EA = (Rs + Rt) & ~7; }});
1517 }
1518 }
1519
1520 0x1: decode FUNCTION_LO {
1521 format StoreIndexedMemory {
1522 0x0: swxc1({{ Mem = Fs_uw; }});
1523 0x1: sdxc1({{ Mem_ud = Fs_ud; }});
1524 0x5: suxc1({{ Mem_ud = Fs_ud; }},
1525 {{ EA = (Rs + Rt) & ~7; }});
1526 }
1527 0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
1528 }
1529
1530 0x3: decode FUNCTION_LO {
1531 0x6: Float64Op::alnv_ps({{
1532 if (Rs<2:0> == 0) {
1533 Fd_ud = Fs_ud;
1534 } else if (Rs<2:0> == 4) {
1535 if (GuestByteOrder == ByteOrder::big)
1536 Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>;
1537 else
1538 Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>;
1539 } else {
1540 Fd_ud = Fd_ud;
1541 }
1542 }});
1543 }
1544
1545 format FloatAccOp {
1546 0x4: decode FUNCTION_LO {
1547 0x0: madd_s({{ Fd_sf = (Fs_sf * Ft_sf) + Fr_sf; }});
1548 0x1: madd_d({{ Fd_df = (Fs_df * Ft_df) + Fr_df; }});
1549 0x6: madd_ps({{
1550 Fd1_sf = (Fs1_df * Ft1_df) + Fr1_df;
1551 Fd2_sf = (Fs2_df * Ft2_df) + Fr2_df;
1552 }});
1553 }
1554
1555 0x5: decode FUNCTION_LO {
1556 0x0: msub_s({{ Fd_sf = (Fs_sf * Ft_sf) - Fr_sf; }});
1557 0x1: msub_d({{ Fd_df = (Fs_df * Ft_df) - Fr_df; }});
1558 0x6: msub_ps({{
1559 Fd1_sf = (Fs1_df * Ft1_df) - Fr1_df;
1560 Fd2_sf = (Fs2_df * Ft2_df) - Fr2_df;
1561 }});
1562 }
1563
1564 0x6: decode FUNCTION_LO {
1565 0x0: nmadd_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) - Fr_sf; }});
1566 0x1: nmadd_d({{ Fd_df = (-1 * Fs_df * Ft_df) - Fr_df; }});
1567 0x6: nmadd_ps({{
1568 Fd1_sf = -((Fs1_df * Ft1_df) + Fr1_df);
1569 Fd2_sf = -((Fs2_df * Ft2_df) + Fr2_df);
1570 }});
1571 }
1572
1573 0x7: decode FUNCTION_LO {
1574 0x0: nmsub_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) + Fr_sf; }});
1575 0x1: nmsub_d({{ Fd_df = (-1 * Fs_df * Ft_df) + Fr_df; }});
1576 0x6: nmsub_ps({{
1577 Fd1_sf = -((Fs1_df * Ft1_df) - Fr1_df);
1578 Fd2_sf = -((Fs2_df * Ft2_df) - Fr2_df);
1579 }});
1580 }
1581 }
1582 }
1583
1584 format Branch {
1585 0x4: beql({{ cond = (Rs_sw == Rt_sw); }}, Likely);
1586 0x5: bnel({{ cond = (Rs_sw != Rt_sw); }}, Likely);
1587 0x6: blezl({{ cond = (Rs_sw <= 0); }}, Likely);
1588 0x7: bgtzl({{ cond = (Rs_sw > 0); }}, Likely);
1589 }
1590 }
1591
1592 0x3: decode OPCODE_LO {
1593 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1594 0x4: decode FUNCTION_HI {
1595 0x0: decode FUNCTION_LO {
1596 0x2: IntOp::mul({{
1597 int64_t temp1 = Rs_sd * Rt_sd;
1598 Rd = temp1<31:0>;
1599 }}, IntMultOp);
1600
1601 format HiLoRdSelValOp {
1602 0x0: madd({{
1603 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) +
1604 (Rs_sd * Rt_sd);
1605 }}, IntMultOp);
1606 0x1: maddu({{
1607 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) +
1608 (Rs_ud * Rt_ud);
1609 }}, IntMultOp);
1610 0x4: msub({{
1611 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) -
1612 (Rs_sd * Rt_sd);
1613 }}, IntMultOp);
1614 0x5: msubu({{
1615 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) -
1616 (Rs_ud * Rt_ud);
1617 }}, IntMultOp);
1618 }
1619 }
1620
1621 0x4: decode FUNCTION_LO {
1622 format BasicOp {
1623 0x0: clz({{
1624 int cnt = 32;
1625 for (int idx = 31; idx >= 0; idx--) {
1626 if (Rs<idx:idx> == 1) {
1627 cnt = 31 - idx;
1628 break;
1629 }
1630 }
1631 Rd = cnt;
1632 }});
1633 0x1: clo({{
1634 int cnt = 32;
1635 for (int idx = 31; idx >= 0; idx--) {
1636 if (Rs<idx:idx> == 0) {
1637 cnt = 31 - idx;
1638 break;
1639 }
1640 }
1641 Rd = cnt;
1642 }});
1643 }
1644 }
1645
1646 0x7: decode FUNCTION_LO {
1647 0x7: FailUnimpl::sdbbp();
1648 }
1649 }
1650
1651 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2
1652 //of the Architecture
1653 0x7: decode FUNCTION_HI {
1654 0x0: decode FUNCTION_LO {
1655 format BasicOp {
1656 0x0: ext({{ Rt = bits(Rs, MSB + LSB, LSB); }});
1657 0x4: ins({{
1658 Rt = bits(Rt, 31, MSB + 1) << (MSB + 1) |
1659 bits(Rs, MSB - LSB, 0) << LSB |
1660 bits(Rt, LSB - 1, 0);
1661 }});
1662 }
1663 }
1664
1665 0x1: decode FUNCTION_LO {
1666 format MT_Control {
1667 0x0: fork({{
1668 forkThread(xc->tcBase(), fault, RD, Rs, Rt);
1669 }}, UserMode);
1670 0x1: yield({{
1671 Rd = yieldThread(xc->tcBase(), fault, Rs_sw,
1672 YQMask);
1673 }}, UserMode);
1674 }
1675
1676 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL)
1677 0x2: decode OP_HI {
1678 0x0: decode OP_LO {
1679 format LoadIndexedMemory {
1680 0x0: lwx({{ Rd = Mem; }});
1681 0x4: lhx({{ Rd = Mem_sh; }});
1682 0x6: lbux({{ Rd = Mem_ub; }});
1683 }
1684 }
1685 }
1686 0x4: DspIntOp::insv({{
1687 int pos = dspctl<5:0>;
1688 int size = dspctl<12:7> - 1;
1689 Rt = insertBits(Rt, pos + size, pos, Rs<size:0>);
1690 }});
1691 }
1692
1693 0x2: decode FUNCTION_LO {
1694
1695 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field
1696 //(DSP ASE MANUAL)
1697 0x0: decode OP_HI {
1698 0x0: decode OP_LO {
1699 format DspIntOp {
1700 0x0: addu_qb({{
1701 Rd = dspAdd(Rs, Rt, SIMD_FMT_QB,
1702 NOSATURATE, UNSIGNED, &dspctl);
1703 }});
1704 0x1: subu_qb({{
1705 Rd = dspSub(Rs, Rt, SIMD_FMT_QB,
1706 NOSATURATE, UNSIGNED, &dspctl);
1707 }});
1708 0x4: addu_s_qb({{
1709 Rd = dspAdd(Rs, Rt, SIMD_FMT_QB,
1710 SATURATE, UNSIGNED, &dspctl);
1711 }});
1712 0x5: subu_s_qb({{
1713 Rd = dspSub(Rs, Rt, SIMD_FMT_QB,
1714 SATURATE, UNSIGNED, &dspctl);
1715 }});
1716 0x6: muleu_s_ph_qbl({{
1717 Rd = dspMuleu(Rs, Rt, MODE_L, &dspctl);
1718 }}, IntMultOp);
1719 0x7: muleu_s_ph_qbr({{
1720 Rd = dspMuleu(Rs, Rt, MODE_R, &dspctl);
1721 }}, IntMultOp);
1722 }
1723 }
1724 0x1: decode OP_LO {
1725 format DspIntOp {
1726 0x0: addu_ph({{
1727 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH,
1728 NOSATURATE, UNSIGNED, &dspctl);
1729 }});
1730 0x1: subu_ph({{
1731 Rd = dspSub(Rs, Rt, SIMD_FMT_PH,
1732 NOSATURATE, UNSIGNED, &dspctl);
1733 }});
1734 0x2: addq_ph({{
1735 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH,
1736 NOSATURATE, SIGNED, &dspctl);
1737 }});
1738 0x3: subq_ph({{
1739 Rd = dspSub(Rs, Rt, SIMD_FMT_PH,
1740 NOSATURATE, SIGNED, &dspctl);
1741 }});
1742 0x4: addu_s_ph({{
1743 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH,
1744 SATURATE, UNSIGNED, &dspctl);
1745 }});
1746 0x5: subu_s_ph({{
1747 Rd = dspSub(Rs, Rt, SIMD_FMT_PH,
1748 SATURATE, UNSIGNED, &dspctl);
1749 }});
1750 0x6: addq_s_ph({{
1751 Rd = dspAdd(Rs, Rt, SIMD_FMT_PH,
1752 SATURATE, SIGNED, &dspctl);
1753 }});
1754 0x7: subq_s_ph({{
1755 Rd = dspSub(Rs, Rt, SIMD_FMT_PH,
1756 SATURATE, SIGNED, &dspctl);
1757 }});
1758 }
1759 }
1760 0x2: decode OP_LO {
1761 format DspIntOp {
1762 0x0: addsc({{
1763 int64_t dresult;
1764 dresult = Rs_ud + Rt_ud;
1765 Rd = dresult<31:0>;
1766 dspctl = insertBits(dspctl, 13, 13,
1767 dresult<32:32>);
1768 }});
1769 0x1: addwc({{
1770 int64_t dresult;
1771 dresult = Rs_sd + Rt_sd + dspctl<13:13>;
1772 Rd = dresult<31:0>;
1773 if (dresult<32:32> != dresult<31:31>)
1774 dspctl = insertBits(dspctl, 20, 20, 1);
1775 }});
1776 0x2: modsub({{
1777 Rd = (Rs_sw == 0) ? Rt_sw<23:8> :
1778 Rs_sw - Rt_sw<7:0>;
1779 }});
1780 0x4: raddu_w_qb({{
1781 Rd = Rs<31:24> + Rs<23:16> +
1782 Rs<15:8> + Rs<7:0>;
1783 }});
1784 0x6: addq_s_w({{
1785 Rd = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W,
1786 SATURATE, SIGNED, &dspctl);
1787 }});
1788 0x7: subq_s_w({{
1789 Rd = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W,
1790 SATURATE, SIGNED, &dspctl);
1791 }});
1792 }
1793 }
1794 0x3: decode OP_LO {
1795 format DspIntOp {
1796 0x4: muleq_s_w_phl({{
1797 Rd = dspMuleq(Rs_sw, Rt_sw,
1798 MODE_L, &dspctl);
1799 }}, IntMultOp);
1800 0x5: muleq_s_w_phr({{
1801 Rd = dspMuleq(Rs_sw, Rt_sw,
1802 MODE_R, &dspctl);
1803 }}, IntMultOp);
1804 0x6: mulq_s_ph({{
1805 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH,
1806 SATURATE, NOROUND, &dspctl);
1807 }}, IntMultOp);
1808 0x7: mulq_rs_ph({{
1809 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH,
1810 SATURATE, ROUND, &dspctl);
1811 }}, IntMultOp);
1812 }
1813 }
1814 }
1815
1816 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field
1817 //(DSP ASE MANUAL)
1818 0x1: decode OP_HI {
1819 0x0: decode OP_LO {
1820 format DspIntOp {
1821 0x0: cmpu_eq_qb({{
1822 dspCmp(Rs, Rt, SIMD_FMT_QB,
1823 UNSIGNED, CMP_EQ, &dspctl);
1824 }});
1825 0x1: cmpu_lt_qb({{
1826 dspCmp(Rs, Rt, SIMD_FMT_QB,
1827 UNSIGNED, CMP_LT, &dspctl);
1828 }});
1829 0x2: cmpu_le_qb({{
1830 dspCmp(Rs, Rt, SIMD_FMT_QB,
1831 UNSIGNED, CMP_LE, &dspctl);
1832 }});
1833 0x3: pick_qb({{
1834 Rd = dspPick(Rs, Rt, SIMD_FMT_QB, &dspctl);
1835 }});
1836 0x4: cmpgu_eq_qb({{
1837 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB,
1838 UNSIGNED, CMP_EQ );
1839 }});
1840 0x5: cmpgu_lt_qb({{
1841 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB,
1842 UNSIGNED, CMP_LT);
1843 }});
1844 0x6: cmpgu_le_qb({{
1845 Rd = dspCmpg(Rs, Rt, SIMD_FMT_QB,
1846 UNSIGNED, CMP_LE);
1847 }});
1848 }
1849 }
1850 0x1: decode OP_LO {
1851 format DspIntOp {
1852 0x0: cmp_eq_ph({{
1853 dspCmp(Rs, Rt, SIMD_FMT_PH,
1854 SIGNED, CMP_EQ, &dspctl);
1855 }});
1856 0x1: cmp_lt_ph({{
1857 dspCmp(Rs, Rt, SIMD_FMT_PH,
1858 SIGNED, CMP_LT, &dspctl);
1859 }});
1860 0x2: cmp_le_ph({{
1861 dspCmp(Rs, Rt, SIMD_FMT_PH,
1862 SIGNED, CMP_LE, &dspctl);
1863 }});
1864 0x3: pick_ph({{
1865 Rd = dspPick(Rs, Rt, SIMD_FMT_PH, &dspctl);
1866 }});
1867 0x4: precrq_qb_ph({{
1868 Rd = Rs<31:24> << 24 | Rs<15:8> << 16 |
1869 Rt<31:24> << 8 | Rt<15:8>;
1870 }});
1871 0x5: precr_qb_ph({{
1872 Rd = Rs<23:16> << 24 | Rs<7:0> << 16 |
1873 Rt<23:16> << 8 | Rt<7:0>;
1874 }});
1875 0x6: packrl_ph({{
1876 Rd = dspPack(Rs, Rt, SIMD_FMT_PH);
1877 }});
1878 0x7: precrqu_s_qb_ph({{
1879 Rd = dspPrecrqu(Rs, Rt, &dspctl);
1880 }});
1881 }
1882 }
1883 0x2: decode OP_LO {
1884 format DspIntOp {
1885 0x4: precrq_ph_w({{
1886 Rd = Rs<31:16> << 16 | Rt<31:16>;
1887 }});
1888 0x5: precrq_rs_ph_w({{
1889 Rd = dspPrecrq(Rs, Rt, SIMD_FMT_W, &dspctl);
1890 }});
1891 }
1892 }
1893 0x3: decode OP_LO {
1894 format DspIntOp {
1895 0x0: cmpgdu_eq_qb({{
1896 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB,
1897 UNSIGNED, CMP_EQ, &dspctl);
1898 }});
1899 0x1: cmpgdu_lt_qb({{
1900 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB,
1901 UNSIGNED, CMP_LT, &dspctl);
1902 }});
1903 0x2: cmpgdu_le_qb({{
1904 Rd = dspCmpgd(Rs, Rt, SIMD_FMT_QB,
1905 UNSIGNED, CMP_LE, &dspctl);
1906 }});
1907 0x6: precr_sra_ph_w({{
1908 Rt = dspPrecrSra(Rt, Rs, RD,
1909 SIMD_FMT_W, NOROUND);
1910 }});
1911 0x7: precr_sra_r_ph_w({{
1912 Rt = dspPrecrSra(Rt, Rs, RD,
1913 SIMD_FMT_W, ROUND);
1914 }});
1915 }
1916 }
1917 }
1918
1919 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field
1920 //(DSP ASE MANUAL)
1921 0x2: decode OP_HI {
1922 0x0: decode OP_LO {
1923 format DspIntOp {
1924 0x1: absq_s_qb({{
1925 Rd = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl);
1926 }});
1927 0x2: repl_qb({{
1928 Rd = RS_RT<7:0> << 24 | RS_RT<7:0> << 16 |
1929 RS_RT<7:0> << 8 | RS_RT<7:0>;
1930 }});
1931 0x3: replv_qb({{
1932 Rd = Rt<7:0> << 24 | Rt<7:0> << 16 |
1933 Rt<7:0> << 8 | Rt<7:0>;
1934 }});
1935 0x4: precequ_ph_qbl({{
1936 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED,
1937 SIMD_FMT_PH, SIGNED, MODE_L);
1938 }});
1939 0x5: precequ_ph_qbr({{
1940 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED,
1941 SIMD_FMT_PH, SIGNED, MODE_R);
1942 }});
1943 0x6: precequ_ph_qbla({{
1944 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED,
1945 SIMD_FMT_PH, SIGNED, MODE_LA);
1946 }});
1947 0x7: precequ_ph_qbra({{
1948 Rd = dspPrece(Rt, SIMD_FMT_QB, UNSIGNED,
1949 SIMD_FMT_PH, SIGNED, MODE_RA);
1950 }});
1951 }
1952 }
1953 0x1: decode OP_LO {
1954 format DspIntOp {
1955 0x1: absq_s_ph({{
1956 Rd = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl);
1957 }});
1958 0x2: repl_ph({{
1959 Rd = (sext<10>(RS_RT))<15:0> << 16 |
1960 (sext<10>(RS_RT))<15:0>;
1961 }});
1962 0x3: replv_ph({{
1963 Rd = Rt<15:0> << 16 | Rt<15:0>;
1964 }});
1965 0x4: preceq_w_phl({{
1966 Rd = dspPrece(Rt, SIMD_FMT_PH, SIGNED,
1967 SIMD_FMT_W, SIGNED, MODE_L);
1968 }});
1969 0x5: preceq_w_phr({{
1970 Rd = dspPrece(Rt, SIMD_FMT_PH, SIGNED,
1971 SIMD_FMT_W, SIGNED, MODE_R);
1972 }});
1973 }
1974 }
1975 0x2: decode OP_LO {
1976 format DspIntOp {
1977 0x1: absq_s_w({{
1978 Rd = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl);
1979 }});
1980 }
1981 }
1982 0x3: decode OP_LO {
1983 0x3: IntOp::bitrev({{
1984 Rd = bitrev(Rt<15:0>);
1985 }});
1986 format DspIntOp {
1987 0x4: preceu_ph_qbl({{
1988 Rd = dspPrece(Rt, SIMD_FMT_QB,
1989 UNSIGNED, SIMD_FMT_PH,
1990 UNSIGNED, MODE_L);
1991 }});
1992 0x5: preceu_ph_qbr({{
1993 Rd = dspPrece(Rt, SIMD_FMT_QB,
1994 UNSIGNED, SIMD_FMT_PH,
1995 UNSIGNED, MODE_R );
1996 }});
1997 0x6: preceu_ph_qbla({{
1998 Rd = dspPrece(Rt, SIMD_FMT_QB,
1999 UNSIGNED, SIMD_FMT_PH,
2000 UNSIGNED, MODE_LA );
2001 }});
2002 0x7: preceu_ph_qbra({{
2003 Rd = dspPrece(Rt, SIMD_FMT_QB,
2004 UNSIGNED, SIMD_FMT_PH,
2005 UNSIGNED, MODE_RA);
2006 }});
2007 }
2008 }
2009 }
2010
2011 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field
2012 //(DSP ASE MANUAL)
2013 0x3: decode OP_HI {
2014 0x0: decode OP_LO {
2015 format DspIntOp {
2016 0x0: shll_qb({{
2017 Rd = dspShll(Rt_sw, RS, SIMD_FMT_QB,
2018 NOSATURATE, UNSIGNED, &dspctl);
2019 }});
2020 0x1: shrl_qb({{
2021 Rd = dspShrl(Rt_sw, RS, SIMD_FMT_QB,
2022 UNSIGNED);
2023 }});
2024 0x2: shllv_qb({{
2025 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB,
2026 NOSATURATE, UNSIGNED, &dspctl);
2027 }});
2028 0x3: shrlv_qb({{
2029 Rd = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB,
2030 UNSIGNED);
2031 }});
2032 0x4: shra_qb({{
2033 Rd = dspShra(Rt_sw, RS, SIMD_FMT_QB,
2034 NOROUND, SIGNED, &dspctl);
2035 }});
2036 0x5: shra_r_qb({{
2037 Rd = dspShra(Rt_sw, RS, SIMD_FMT_QB,
2038 ROUND, SIGNED, &dspctl);
2039 }});
2040 0x6: shrav_qb({{
2041 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB,
2042 NOROUND, SIGNED, &dspctl);
2043 }});
2044 0x7: shrav_r_qb({{
2045 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB,
2046 ROUND, SIGNED, &dspctl);
2047 }});
2048 }
2049 }
2050 0x1: decode OP_LO {
2051 format DspIntOp {
2052 0x0: shll_ph({{
2053 Rd = dspShll(Rt, RS, SIMD_FMT_PH,
2054 NOSATURATE, SIGNED, &dspctl);
2055 }});
2056 0x1: shra_ph({{
2057 Rd = dspShra(Rt_sw, RS, SIMD_FMT_PH,
2058 NOROUND, SIGNED, &dspctl);
2059 }});
2060 0x2: shllv_ph({{
2061 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH,
2062 NOSATURATE, SIGNED, &dspctl);
2063 }});
2064 0x3: shrav_ph({{
2065 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH,
2066 NOROUND, SIGNED, &dspctl);
2067 }});
2068 0x4: shll_s_ph({{
2069 Rd = dspShll(Rt_sw, RS, SIMD_FMT_PH,
2070 SATURATE, SIGNED, &dspctl);
2071 }});
2072 0x5: shra_r_ph({{
2073 Rd = dspShra(Rt_sw, RS, SIMD_FMT_PH,
2074 ROUND, SIGNED, &dspctl);
2075 }});
2076 0x6: shllv_s_ph({{
2077 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH,
2078 SATURATE, SIGNED, &dspctl);
2079 }});
2080 0x7: shrav_r_ph({{
2081 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH,
2082 ROUND, SIGNED, &dspctl);
2083 }});
2084 }
2085 }
2086 0x2: decode OP_LO {
2087 format DspIntOp {
2088 0x4: shll_s_w({{
2089 Rd = dspShll(Rt_sw, RS, SIMD_FMT_W,
2090 SATURATE, SIGNED, &dspctl);
2091 }});
2092 0x5: shra_r_w({{
2093 Rd = dspShra(Rt_sw, RS, SIMD_FMT_W,
2094 ROUND, SIGNED, &dspctl);
2095 }});
2096 0x6: shllv_s_w({{
2097 Rd = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W,
2098 SATURATE, SIGNED, &dspctl);
2099 }});
2100 0x7: shrav_r_w({{
2101 Rd = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W,
2102 ROUND, SIGNED, &dspctl);
2103 }});
2104 }
2105 }
2106 0x3: decode OP_LO {
2107 format DspIntOp {
2108 0x1: shrl_ph({{
2109 Rd = dspShrl(Rt_sw, RS, SIMD_FMT_PH,
2110 UNSIGNED);
2111 }});
2112 0x3: shrlv_ph({{
2113 Rd = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH,
2114 UNSIGNED);
2115 }});
2116 }
2117 }
2118 }
2119 }
2120
2121 0x3: decode FUNCTION_LO {
2122
2123 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field
2124 //(DSP ASE Rev2 Manual)
2125 0x0: decode OP_HI {
2126 0x0: decode OP_LO {
2127 format DspIntOp {
2128 0x0: adduh_qb({{
2129 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2130 NOROUND, UNSIGNED);
2131 }});
2132 0x1: subuh_qb({{
2133 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2134 NOROUND, UNSIGNED);
2135 }});
2136 0x2: adduh_r_qb({{
2137 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2138 ROUND, UNSIGNED);
2139 }});
2140 0x3: subuh_r_qb({{
2141 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2142 ROUND, UNSIGNED);
2143 }});
2144 }
2145 }
2146 0x1: decode OP_LO {
2147 format DspIntOp {
2148 0x0: addqh_ph({{
2149 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2150 NOROUND, SIGNED);
2151 }});
2152 0x1: subqh_ph({{
2153 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2154 NOROUND, SIGNED);
2155 }});
2156 0x2: addqh_r_ph({{
2157 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2158 ROUND, SIGNED);
2159 }});
2160 0x3: subqh_r_ph({{
2161 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2162 ROUND, SIGNED);
2163 }});
2164 0x4: mul_ph({{
2165 Rd = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH,
2166 NOSATURATE, &dspctl);
2167 }}, IntMultOp);
2168 0x6: mul_s_ph({{
2169 Rd = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH,
2170 SATURATE, &dspctl);
2171 }}, IntMultOp);
2172 }
2173 }
2174 0x2: decode OP_LO {
2175 format DspIntOp {
2176 0x0: addqh_w({{
2177 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W,
2178 NOROUND, SIGNED);
2179 }});
2180 0x1: subqh_w({{
2181 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W,
2182 NOROUND, SIGNED);
2183 }});
2184 0x2: addqh_r_w({{
2185 Rd = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W,
2186 ROUND, SIGNED);
2187 }});
2188 0x3: subqh_r_w({{
2189 Rd = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W,
2190 ROUND, SIGNED);
2191 }});
2192 0x6: mulq_s_w({{
2193 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W,
2194 SATURATE, NOROUND, &dspctl);
2195 }}, IntMultOp);
2196 0x7: mulq_rs_w({{
2197 Rd = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W,
2198 SATURATE, ROUND, &dspctl);
2199 }}, IntMultOp);
2200 }
2201 }
2202 }
2203 }
2204
2205 //Table A-10 MIPS32 BSHFL Encoding of sa Field
2206 0x4: decode SA {
2207 format BasicOp {
2208 0x02: wsbh({{
2209 Rd = Rt<23:16> << 24 | Rt<31:24> << 16 |
2210 Rt<7:0> << 8 | Rt<15:8>;
2211 }});
2212 0x10: seb({{ Rd = Rt_sb; }});
2213 0x18: seh({{ Rd = Rt_sh; }});
2214 }
2215 }
2216
2217 0x6: decode FUNCTION_LO {
2218
2219 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field
2220 //(DSP ASE MANUAL)
2221 0x0: decode OP_HI {
2222 0x0: decode OP_LO {
2223 format DspHiLoOp {
2224 0x0: dpa_w_ph({{
2225 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST,
2226 SIMD_FMT_PH, SIGNED, MODE_L);
2227 }}, IntMultOp);
2228 0x1: dps_w_ph({{
2229 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST,
2230 SIMD_FMT_PH, SIGNED, MODE_L);
2231 }}, IntMultOp);
2232 0x2: mulsa_w_ph({{
2233 dspac = dspMulsa(dspac, Rs_sw, Rt_sw,
2234 ACDST, SIMD_FMT_PH );
2235 }}, IntMultOp);
2236 0x3: dpau_h_qbl({{
2237 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST,
2238 SIMD_FMT_QB, UNSIGNED, MODE_L);
2239 }}, IntMultOp);
2240 0x4: dpaq_s_w_ph({{
2241 dspac = dspDpaq(dspac, Rs_sw, Rt_sw,
2242 ACDST, SIMD_FMT_PH,
2243 SIMD_FMT_W, NOSATURATE,
2244 MODE_L, &dspctl);
2245 }}, IntMultOp);
2246 0x5: dpsq_s_w_ph({{
2247 dspac = dspDpsq(dspac, Rs_sw, Rt_sw,
2248 ACDST, SIMD_FMT_PH,
2249 SIMD_FMT_W, NOSATURATE,
2250 MODE_L, &dspctl);
2251 }}, IntMultOp);
2252 0x6: mulsaq_s_w_ph({{
2253 dspac = dspMulsaq(dspac, Rs_sw, Rt_sw,
2254 ACDST, SIMD_FMT_PH,
2255 &dspctl);
2256 }}, IntMultOp);
2257 0x7: dpau_h_qbr({{
2258 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST,
2259 SIMD_FMT_QB, UNSIGNED, MODE_R);
2260 }}, IntMultOp);
2261 }
2262 }
2263 0x1: decode OP_LO {
2264 format DspHiLoOp {
2265 0x0: dpax_w_ph({{
2266 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST,
2267 SIMD_FMT_PH, SIGNED, MODE_X);
2268 }}, IntMultOp);
2269 0x1: dpsx_w_ph({{
2270 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST,
2271 SIMD_FMT_PH, SIGNED, MODE_X);
2272 }}, IntMultOp);
2273 0x3: dpsu_h_qbl({{
2274 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST,
2275 SIMD_FMT_QB, UNSIGNED, MODE_L);
2276 }}, IntMultOp);
2277 0x4: dpaq_sa_l_w({{
2278 dspac = dspDpaq(dspac, Rs_sw, Rt_sw,
2279 ACDST, SIMD_FMT_W,
2280 SIMD_FMT_L, SATURATE,
2281 MODE_L, &dspctl);
2282 }}, IntMultOp);
2283 0x5: dpsq_sa_l_w({{
2284 dspac = dspDpsq(dspac, Rs_sw, Rt_sw,
2285 ACDST, SIMD_FMT_W,
2286 SIMD_FMT_L, SATURATE,
2287 MODE_L, &dspctl);
2288 }}, IntMultOp);
2289 0x7: dpsu_h_qbr({{
2290 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST,
2291 SIMD_FMT_QB, UNSIGNED, MODE_R);
2292 }}, IntMultOp);
2293 }
2294 }
2295 0x2: decode OP_LO {
2296 format DspHiLoOp {
2297 0x0: maq_sa_w_phl({{
2298 dspac = dspMaq(dspac, Rs, Rt,
2299 ACDST, SIMD_FMT_PH,
2300 MODE_L, SATURATE, &dspctl);
2301 }}, IntMultOp);
2302 0x2: maq_sa_w_phr({{
2303 dspac = dspMaq(dspac, Rs, Rt,
2304 ACDST, SIMD_FMT_PH,
2305 MODE_R, SATURATE, &dspctl);
2306 }}, IntMultOp);
2307 0x4: maq_s_w_phl({{
2308 dspac = dspMaq(dspac, Rs, Rt,
2309 ACDST, SIMD_FMT_PH,
2310 MODE_L, NOSATURATE, &dspctl);
2311 }}, IntMultOp);
2312 0x6: maq_s_w_phr({{
2313 dspac = dspMaq(dspac, Rs, Rt,
2314 ACDST, SIMD_FMT_PH,
2315 MODE_R, NOSATURATE, &dspctl);
2316 }}, IntMultOp);
2317 }
2318 }
2319 0x3: decode OP_LO {
2320 format DspHiLoOp {
2321 0x0: dpaqx_s_w_ph({{
2322 dspac = dspDpaq(dspac, Rs_sw, Rt_sw,
2323 ACDST, SIMD_FMT_PH,
2324 SIMD_FMT_W, NOSATURATE,
2325 MODE_X, &dspctl);
2326 }}, IntMultOp);
2327 0x1: dpsqx_s_w_ph({{
2328 dspac = dspDpsq(dspac, Rs_sw, Rt_sw,
2329 ACDST, SIMD_FMT_PH,
2330 SIMD_FMT_W, NOSATURATE,
2331 MODE_X, &dspctl);
2332 }}, IntMultOp);
2333 0x2: dpaqx_sa_w_ph({{
2334 dspac = dspDpaq(dspac, Rs_sw, Rt_sw,
2335 ACDST, SIMD_FMT_PH,
2336 SIMD_FMT_W, SATURATE,
2337 MODE_X, &dspctl);
2338 }}, IntMultOp);
2339 0x3: dpsqx_sa_w_ph({{
2340 dspac = dspDpsq(dspac, Rs_sw, Rt_sw,
2341 ACDST, SIMD_FMT_PH,
2342 SIMD_FMT_W, SATURATE,
2343 MODE_X, &dspctl);
2344 }}, IntMultOp);
2345 }
2346 }
2347 }
2348
2349 //Table 3.3 MIPS32 APPEND Encoding of the op Field
2350 0x1: decode OP_HI {
2351 0x0: decode OP_LO {
2352 format IntOp {
2353 0x0: append({{
2354 Rt = (Rt << RD) | bits(Rs, RD - 1, 0);
2355 }});
2356 0x1: prepend({{
2357 Rt = (Rt >> RD) |
2358 (bits(Rs, RD - 1, 0) << (32 - RD));
2359 }});
2360 }
2361 }
2362 0x2: decode OP_LO {
2363 format IntOp {
2364 0x0: balign({{
2365 Rt = (Rt << (8 * BP)) | (Rs >> (8 * (4 - BP)));
2366 }});
2367 }
2368 }
2369 }
2370
2371 }
2372 0x7: decode FUNCTION_LO {
2373
2374 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field
2375 //(DSP ASE MANUAL)
2376 0x0: decode OP_HI {
2377 0x0: decode OP_LO {
2378 format DspHiLoOp {
2379 0x0: extr_w({{
2380 Rt = dspExtr(dspac, SIMD_FMT_W, RS,
2381 NOROUND, NOSATURATE, &dspctl);
2382 }});
2383 0x1: extrv_w({{
2384 Rt = dspExtr(dspac, SIMD_FMT_W, Rs,
2385 NOROUND, NOSATURATE, &dspctl);
2386 }});
2387 0x2: extp({{
2388 Rt = dspExtp(dspac, RS, &dspctl);
2389 }});
2390 0x3: extpv({{
2391 Rt = dspExtp(dspac, Rs, &dspctl);
2392 }});
2393 0x4: extr_r_w({{
2394 Rt = dspExtr(dspac, SIMD_FMT_W, RS,
2395 ROUND, NOSATURATE, &dspctl);
2396 }});
2397 0x5: extrv_r_w({{
2398 Rt = dspExtr(dspac, SIMD_FMT_W, Rs,
2399 ROUND, NOSATURATE, &dspctl);
2400 }});
2401 0x6: extr_rs_w({{
2402 Rt = dspExtr(dspac, SIMD_FMT_W, RS,
2403 ROUND, SATURATE, &dspctl);
2404 }});
2405 0x7: extrv_rs_w({{
2406 Rt = dspExtr(dspac, SIMD_FMT_W, Rs,
2407 ROUND, SATURATE, &dspctl);
2408 }});
2409 }
2410 }
2411 0x1: decode OP_LO {
2412 format DspHiLoOp {
2413 0x2: extpdp({{
2414 Rt = dspExtpd(dspac, RS, &dspctl);
2415 }});
2416 0x3: extpdpv({{
2417 Rt = dspExtpd(dspac, Rs, &dspctl);
2418 }});
2419 0x6: extr_s_h({{
2420 Rt = dspExtr(dspac, SIMD_FMT_PH, RS,
2421 NOROUND, SATURATE, &dspctl);
2422 }});
2423 0x7: extrv_s_h({{
2424 Rt = dspExtr(dspac, SIMD_FMT_PH, Rs,
2425 NOROUND, SATURATE, &dspctl);
2426 }});
2427 }
2428 }
2429 0x2: decode OP_LO {
2430 format DspIntOp {
2431 0x2: rddsp({{
2432 Rd = readDSPControl(&dspctl, RDDSPMASK);
2433 }});
2434 0x3: wrdsp({{
2435 writeDSPControl(&dspctl, Rs, WRDSPMASK);
2436 }});
2437 }
2438 }
2439 0x3: decode OP_LO {
2440 format DspHiLoOp {
2441 0x2: shilo({{
2442 if ((int64_t)sext<6>(HILOSA) < 0) {
2443 dspac = (uint64_t)dspac <<
2444 -sext<6>(HILOSA);
2445 } else {
2446 dspac = (uint64_t)dspac >>
2447 sext<6>(HILOSA);
2448 }
2449 }});
2450 0x3: shilov({{
2451 if ((int64_t)sext<6>(Rs_sw<5:0>) < 0) {
2452 dspac = (uint64_t)dspac <<
2453 -sext<6>(Rs_sw<5:0>);
2454 } else {
2455 dspac = (uint64_t)dspac >>
2456 sext<6>(Rs_sw<5:0>);
2457 }
2458 }});
2459 0x7: mthlip({{
2460 dspac = dspac << 32;
2461 dspac |= Rs;
2462 dspctl = insertBits(dspctl, 5, 0,
2463 dspctl<5:0> + 32);
2464 }});
2465 }
2466 }
2467 }
2468 0x3: decode OP default FailUnimpl::rdhwr() {
2469 0x0: decode FullSystemInt {
2470 0: decode RD {
2471 29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
2472 }
2473 }
2474 }
2475 }
2476 }
2477 }
2478
2479 0x4: decode OPCODE_LO {
2480 format LoadMemory {
2481 0x0: lb({{ Rt = Mem_sb; }});
2482 0x1: lh({{ Rt = Mem_sh; }});
2483 0x3: lw({{ Rt = Mem_sw; }});
2484 0x4: lbu({{ Rt = Mem_ub;}});
2485 0x5: lhu({{ Rt = Mem_uh; }});
2486 }
2487
2488 format LoadUnalignedMemory {
2489 0x2: lwl({{
2490 uint32_t mem_shift = 24 - (8 * byte_offset);
2491 Rt = mem_word << mem_shift | (Rt & mask(mem_shift));
2492 }});
2493 0x6: lwr({{
2494 uint32_t mem_shift = 8 * byte_offset;
2495 Rt = (Rt & (mask(mem_shift) << (32 - mem_shift))) |
2496 (mem_word >> mem_shift);
2497 }});
2498 }
2499 }
2500
2501 0x5: decode OPCODE_LO {
2502 format StoreMemory {
2503 0x0: sb({{ Mem_ub = Rt<7:0>; }});
2504 0x1: sh({{ Mem_uh = Rt<15:0>; }});
2505 0x3: sw({{ Mem = Rt<31:0>; }});
2506 }
2507
2508 format StoreUnalignedMemory {
2509 0x2: swl({{
2510 uint32_t reg_shift = 24 - (8 * byte_offset);
2511 uint32_t mem_shift = 32 - reg_shift;
2512 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) |
2513 (Rt >> reg_shift);
2514 }});
2515 0x6: swr({{
2516 uint32_t reg_shift = 8 * byte_offset;
2517 mem_word = Rt << reg_shift |
2518 (mem_word & (mask(reg_shift)));
2519 }});
2520 }
2521 format CP0Control {
2522 0x7: cache({{
2523 //Addr CacheEA = Rs + OFFSET;
2524 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
2525 }});
2526 }
2527 }
2528
2529 0x6: decode OPCODE_LO {
2530 format LoadMemory {
2531 0x0: ll({{ Rt = Mem; }}, mem_flags=LLSC);
2532 0x1: lwc1({{ Ft_uw = Mem; }});
2533 0x5: ldc1({{ Ft_ud = Mem_ud; }});
2534 }
2535 0x2: CP2Unimpl::lwc2();
2536 0x6: CP2Unimpl::ldc2();
2537 0x3: Prefetch::pref();
2538 }
2539
2540
2541 0x7: decode OPCODE_LO {
2542 0x0: StoreCond::sc({{ Mem = Rt; }},
2543 {{ uint64_t tmp = write_result;
2544 Rt = (tmp == 0 || tmp == 1) ? tmp : Rt;
2545 }}, mem_flags=LLSC,
2546 inst_flags = IsStoreConditional);
2547 format StoreMemory {
2548 0x1: swc1({{ Mem = Ft_uw; }});
2549 0x5: sdc1({{ Mem_ud = Ft_ud; }});
2550 }
2551 0x2: CP2Unimpl::swc2();
2552 0x6: CP2Unimpl::sdc2();
2553 }
2554 }
2555
2556