3 // Copyright (c) 2006 The Regents of The University of Michigan
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Korey Sewell
31 ////////////////////////////////////////////////////////////////////
33 // The actual MIPS32 ISA decoder
34 // -----------------------------
35 // The following instructions are specified in the MIPS32 ISA
36 // Specification. Decoding closely follows the style specified
37 // in the MIPS32 ISA specification document starting with Table
38 // A-2 (document available @ www.mips.com)
40 decode OPCODE_HI default Unknown::unknown() {
42 0x0: decode OPCODE_LO {
43 0x0: decode FUNCTION_HI {
44 0x0: decode FUNCTION_LO {
47 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }});
48 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }});
53 //Table A-3 Note: "Specific encodings of the rd, rs, and
54 //rt fields are used to distinguish SLL, SSNOP, and EHB
58 0x0: decode SA default Nop::nop(){
59 0x1: WarnUnimpl::ssnop();
60 0x3: WarnUnimpl::ehb();
62 default: sll({{ Rd = Rt.uw << SA; }});
68 0: srl({{ Rd = Rt.uw >> SA; }});
70 //Hardcoded assuming 32-bit ISA, probably need parameter here
71 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
77 uint32_t temp = Rt >> SA;
78 if ( (Rt & 0x80000000) > 0 ) {
79 uint32_t mask = 0x80000000;
80 for(int i=0; i < SA; i++) {
89 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
92 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
94 //Hardcoded assuming 32-bit ISA, probably need parameter here
95 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
99 int shift_amt = Rs<4:0>;
101 uint32_t temp = Rt >> shift_amt;
103 if ( (Rt & 0x80000000) > 0 ) {
104 uint32_t mask = 0x80000000;
105 for(int i=0; i < shift_amt; i++) {
116 0x1: decode FUNCTION_LO {
117 //Table A-3 Note: "Specific encodings of the hint field are
118 //used to distinguish JR from JR.HB and JALR from JALR.HB"
121 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
122 default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
126 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall, Link
128 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall,
134 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
135 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
136 0x4: syscall({{ xc->syscall(R2); }}, IsNonSpeculative);
137 0x7: sync({{ ; }}, IsMemBarrier);
145 0x2: decode FUNCTION_LO {
147 0x0: mfhi({{ Rd = HI; }});
148 0x1: mthi({{ HI = Rs; }});
149 0x2: mflo({{ Rd = LO; }});
150 0x3: mtlo({{ LO = Rs; }});
154 0x3: decode FUNCTION_LO {
156 0x0: mult({{ val = Rs.sd * Rt.sd; }});
157 0x1: multu({{ val = Rs.ud * Rt.ud; }});
161 0x2: div({{ if (Rt.sd != 0) {
166 0x3: divu({{ if (Rt.ud != 0) {
175 0x0: decode FUNCTION_LO {
177 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
178 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
179 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
180 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
181 0x4: and({{ Rd = Rs & Rt;}});
182 0x5: or({{ Rd = Rs | Rt;}});
183 0x6: xor({{ Rd = Rs ^ Rt;}});
184 0x7: nor({{ Rd = ~(Rs | Rt);}});
190 0x0: decode FUNCTION_LO {
192 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
193 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
198 0x6: decode FUNCTION_LO {
200 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
201 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
202 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
203 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
204 0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
205 0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
210 0x1: decode REGIMM_HI {
211 0x0: decode REGIMM_LO {
213 0x0: bltz({{ cond = (Rs.sw < 0); }});
214 0x1: bgez({{ cond = (Rs.sw >= 0); }});
215 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely);
216 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely);
220 0x1: decode REGIMM_LO {
222 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
223 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
224 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
225 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
226 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
227 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
231 0x2: decode REGIMM_LO {
233 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link);
235 0x0: bal ({{ cond = 1; }}, IsCall, Link);
236 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link);
238 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely);
239 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely);
243 0x3: decode REGIMM_LO {
251 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
252 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall,
258 0x0: b({{ cond = 1; }});
259 default: beq({{ cond = (Rs.sw == Rt.sw); }});
261 0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
262 0x6: blez({{ cond = (Rs.sw <= 0); }});
263 0x7: bgtz({{ cond = (Rs.sw > 0); }});
267 0x1: decode OPCODE_LO {
269 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
270 0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
271 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
272 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
273 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
274 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
275 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
278 0x0: lui({{ Rt = imm << 16}});
283 0x2: decode OPCODE_LO {
284 //Table A-11 MIPS32 COP0 Encoding of rs Field
288 0x0: mfc0({{ Rt = xc->readMiscReg(RD << 5 | SEL); }});
289 0x4: mtc0({{ xc->setMiscReg(RD << 5 | SEL, Rt); }});
317 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
318 0x1: decode FUNCTION {
332 //Table A-13 MIPS32 COP1 Encoding of rs Field
338 0x0: mfc1 ({{ Rt.uw = Fs.uw; }});
347 Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23;
350 Rt = 0 | (FCSR & 0x0003F07C);
353 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003);
359 panic("FP Control Value (%d) Not Valid");
363 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
365 0x4: mtc1 ({{ Fs.uw = Rt.uw; }});
371 FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25
372 | (FCSR & 0x01000000) // bit 24
373 | (FCSR & 0x004FFFFF);// bit 22...0
377 FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18
378 | Rt.uw<17:12> << 12 // bit 17...12
379 | (FCSR & 0x00000F80) << 7// bit 11...7
380 | Rt.uw<6:2> << 2 // bit 6...2
381 | (FCSR & 0x00000002); // bit 1...0
385 FCSR = 0 | (FCSR & 0xFE000000) // move 31...25
386 | Rt.uw<2:2> << 24 // bit 24
387 | (FCSR & 0x00FFF000) << 23// bit 23...12
388 | Rt.uw<11:7> << 7 // bit 24
390 | Rt.uw<1:0>;// bit 22...0
398 panic("FP Control Value (%d) Not Available. Ignoring Access to"
399 "Floating Control Status Register", FS);
404 uint64_t fs_hi = Rt.uw;
405 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF;
406 Fs.ud = (fs_hi << 32) | fs_lo;
415 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
417 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
421 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
423 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
432 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
433 //(( single-precision floating point))
434 0x0: decode FUNCTION_HI {
435 0x0: decode FUNCTION_LO {
437 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}});
438 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}});
439 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}});
440 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}});
441 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}});
442 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}});
443 0x7: neg_s({{ Fd.sf = -Fs.sf;}});
446 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}});
449 0x1: decode FUNCTION_LO {
450 format FloatConvertOp {
451 0x0: round_l_s({{ val = Fs.sf; }}, ToLong,
453 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong,
455 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong,
457 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong,
459 0x4: round_w_s({{ val = Fs.sf; }}, ToWord,
461 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord,
463 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord,
465 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord,
470 0x2: decode FUNCTION_LO {
473 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }});
474 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }});
479 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
480 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
484 0x5: recip_s({{ Fd = 1 / Fs; }});
485 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
489 0x4: decode FUNCTION_LO {
490 format FloatConvertOp {
491 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble);
492 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord);
493 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong);
496 0x6: FloatOp::cvt_ps_s({{
497 Fd.ud = (uint64_t) Fs.uw << 32 |
502 0x6: decode FUNCTION_LO {
503 format FloatCompareOp {
504 0x0: c_f_s({{ cond = 0; }}, SinglePrecision,
506 0x1: c_un_s({{ cond = 0; }}, SinglePrecision,
508 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }},
510 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }},
512 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }},
514 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }},
516 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }},
518 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }},
523 0x7: decode FUNCTION_LO {
524 format FloatCompareOp {
525 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision,
526 UnorderedFalse, QnanException);
527 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision,
528 UnorderedTrue, QnanException);
529 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}},
530 UnorderedFalse, QnanException);
531 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }},
532 UnorderedTrue, QnanException);
533 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }},
534 UnorderedFalse, QnanException);
535 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }},
536 UnorderedTrue, QnanException);
537 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }},
538 UnorderedFalse, QnanException);
539 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }},
540 UnorderedTrue, QnanException);
545 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
546 0x1: decode FUNCTION_HI {
547 0x0: decode FUNCTION_LO {
549 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }});
550 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }});
551 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }});
552 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }});
553 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }});
554 0x5: abs_d({{ Fd.df = fabs(Fs.df); }});
555 0x7: neg_d({{ Fd.df = -1 * Fs.df; }});
558 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }});
561 0x1: decode FUNCTION_LO {
562 format FloatConvertOp {
563 0x0: round_l_d({{ val = Fs.df; }}, ToLong,
565 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong,
567 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong,
569 0x3: floor_l_d({{ val = Fs.df; }}, ToLong,
571 0x4: round_w_d({{ val = Fs.df; }}, ToWord,
573 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord,
575 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord,
577 0x7: floor_w_d({{ val = Fs.df; }}, ToWord,
582 0x2: decode FUNCTION_LO {
585 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ?
588 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ?
595 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }});
596 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }});
600 0x5: recip_d({{ Fd.df = 1 / Fs.df }});
601 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
605 0x4: decode FUNCTION_LO {
606 format FloatConvertOp {
607 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
608 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
609 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
613 0x6: decode FUNCTION_LO {
614 format FloatCompareOp {
615 0x0: c_f_d({{ cond = 0; }}, DoublePrecision,
617 0x1: c_un_d({{ cond = 0; }}, DoublePrecision,
619 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }},
621 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }},
623 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }},
625 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }},
627 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }},
629 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }},
634 0x7: decode FUNCTION_LO {
635 format FloatCompareOp {
636 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision,
637 UnorderedFalse, QnanException);
638 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision,
639 UnorderedTrue, QnanException);
640 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }},
641 UnorderedFalse, QnanException);
642 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }},
643 UnorderedTrue, QnanException);
644 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }},
645 UnorderedFalse, QnanException);
646 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }},
647 UnorderedTrue, QnanException);
648 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }},
649 UnorderedFalse, QnanException);
650 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }},
651 UnorderedTrue, QnanException);
656 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
657 0x4: decode FUNCTION {
658 format FloatConvertOp {
659 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
660 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
661 0x26: FailUnimpl::cvt_ps_w();
665 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
666 //Note: "1. Format type L is legal only if 64-bit floating point operations
668 0x5: decode FUNCTION_HI {
669 format FloatConvertOp {
670 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
671 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
672 0x26: FailUnimpl::cvt_ps_l();
676 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
677 //Note: "1. Format type PS is legal only if 64-bit floating point operations
679 0x6: decode FUNCTION_HI {
680 0x0: decode FUNCTION_LO {
683 Fd1.sf = Fs1.sf + Ft2.sf;
684 Fd2.sf = Fs2.sf + Ft2.sf;
687 Fd1.sf = Fs1.sf - Ft2.sf;
688 Fd2.sf = Fs2.sf - Ft2.sf;
691 Fd1.sf = Fs1.sf * Ft2.sf;
692 Fd2.sf = Fs2.sf * Ft2.sf;
695 Fd1.sf = fabs(Fs1.sf);
696 Fd2.sf = fabs(Fs2.sf);
709 0x2: decode FUNCTION_LO {
713 Fd1 = (getCondCode(FCSR, CC) == 0) ?
715 Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
719 Fd2 = (getCondCode(FCSR, CC) == 1) ?
721 Fd2 = (getCondCode(FCSR, CC+1) == 1) ?
729 Fd1 = (getCondCode(FCSR, CC) == 0) ?
731 Fd2 = (getCondCode(FCSR, CC) == 0) ?
735 Fd1 = (getCondCode(FCSR, CC) == 1) ?
737 Fd2 = (getCondCode(FCSR, CC) == 1) ?
744 0x4: decode FUNCTION_LO {
745 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
748 0x5: decode FUNCTION_LO {
749 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }});
752 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
755 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
758 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
761 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
767 0x6: decode FUNCTION_LO {
768 format FloatPSCompareOp {
769 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
771 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
773 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
774 {{ cond2 = (Fs2.sf == Ft2.sf); }},
776 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
777 {{ cond2 = (Fs2.sf == Ft2.sf); }},
779 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
780 {{ cond2 = (Fs2.sf < Ft2.sf); }},
782 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }},
783 {{ cond2 = (Fs2.sf < Ft2.sf); }},
785 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }},
786 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
788 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
789 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
794 0x7: decode FUNCTION_LO {
795 format FloatPSCompareOp {
796 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
797 UnorderedFalse, QnanException);
798 0x1: c_ngle_ps({{ cond1 = 0; }},
800 UnorderedTrue, QnanException);
801 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
802 {{ cond2 = (Fs2.sf == Ft2.sf); }},
803 UnorderedFalse, QnanException);
804 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
805 {{ cond2 = (Fs2.sf == Ft2.sf); }},
806 UnorderedTrue, QnanException);
807 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
808 {{ cond2 = (Fs2.sf < Ft2.sf); }},
809 UnorderedFalse, QnanException);
810 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
811 {{ cond2 = (Fs2.sf < Ft2.sf); }},
812 UnorderedTrue, QnanException);
813 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
814 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
815 UnorderedFalse, QnanException);
816 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
817 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
818 UnorderedTrue, QnanException);
826 //Table A-19 MIPS32 COP2 Encoding of rs Field
854 //Table A-20 MIPS64 COP1X Encoding of Function Field 1
855 //Note: "COP1X instructions are legal only if 64-bit floating point
856 //operations are enabled."
857 0x3: decode FUNCTION_HI {
858 0x0: decode FUNCTION_LO {
859 format LoadIndexedMemory {
860 0x0: lwxc1({{ Fd.uw = Mem.uw;}});
861 0x1: ldxc1({{ Fd.ud = Mem.ud;}});
862 0x5: luxc1({{ Fd.ud = Mem.ud;}},
863 {{ EA = (Rs + Rt) & ~7; }});
867 0x1: decode FUNCTION_LO {
868 format StoreIndexedMemory {
869 0x0: swxc1({{ Mem.uw = Fs.uw;}});
870 0x1: sdxc1({{ Mem.ud = Fs.ud;}});
871 0x5: suxc1({{ Mem.ud = Fs.ud;}},
872 {{ EA = (Rs + Rt) & ~7; }});
875 0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
878 0x3: decode FUNCTION_LO {
879 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) {
881 } else if (Rs<2:0> == 4) {
882 #if BYTE_ORDER == BIG_ENDIAN
883 Fd.ud = Fs.ud<31:0> << 32 |
885 #elif BYTE_ORDER == LITTLE_ENDIAN
886 Fd.ud = Ft.ud<31:0> << 32 |
896 0x4: decode FUNCTION_LO {
897 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }});
898 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }});
900 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df;
901 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df;
905 0x5: decode FUNCTION_LO {
906 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }});
907 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }});
909 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df;
910 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df;
914 0x6: decode FUNCTION_LO {
915 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
916 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }});
918 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df);
919 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df);
923 0x7: decode FUNCTION_LO {
924 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
925 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }});
927 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df);
928 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df);
936 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely);
937 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely);
938 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely);
939 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely);
943 0x3: decode OPCODE_LO {
944 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
945 0x4: decode FUNCTION_HI {
946 0x0: decode FUNCTION_LO {
947 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
952 0x0: madd({{ val = ((int64_t) HI << 32 | LO) +
955 0x1: maddu({{ val = ((uint64_t) HI << 32 | LO) +
958 0x4: msub({{ val = ((int64_t) HI << 32 | LO) -
961 0x5: msubu({{ val = ((uint64_t) HI << 32 | LO) -
967 0x4: decode FUNCTION_LO {
969 0x0: clz({{ int cnt = 32;
970 for (int idx = 31; idx >= 0; idx--) {
971 if( Rs<idx:idx> == 1) {
978 0x1: clo({{ int cnt = 32;
979 for (int idx = 31; idx >= 0; idx--) {
980 if( Rs<idx:idx> == 0) {
990 0x7: decode FUNCTION_LO {
991 0x7: FailUnimpl::sdbbp();
995 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2
996 //of the Architecture
997 0x7: decode FUNCTION_HI {
998 0x0: decode FUNCTION_LO {
1000 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }});
1001 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) |
1002 bits(Rs.uw, MSB-LSB, 0) << LSB |
1003 bits(Rt.uw, LSB-1, 0);
1008 0x1: decode FUNCTION_LO {
1015 //Table A-10 MIPS32 BSHFL Encoding of sa Field
1018 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 |
1019 Rt.uw<31:24> << 16 |
1023 0x10: seb({{ Rd.sw = Rt.sb; }});
1024 0x18: seh({{ Rd.sw = Rt.sh; }});
1028 0x6: decode FUNCTION_LO {
1029 0x7: FailUnimpl::rdhwr();
1034 0x4: decode OPCODE_LO {
1036 0x0: lb({{ Rt.sw = Mem.sb; }});
1037 0x1: lh({{ Rt.sw = Mem.sh; }});
1038 0x3: lw({{ Rt.sw = Mem.sw; }});
1039 0x4: lbu({{ Rt.uw = Mem.ub; }});
1040 0x5: lhu({{ Rt.uw = Mem.uh; }});
1043 format LoadUnalignedMemory {
1044 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
1045 Rt.uw = mem_word << mem_shift |
1046 Rt.uw & mask(mem_shift);
1048 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
1049 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
1050 mem_word >> mem_shift;
1055 0x5: decode OPCODE_LO {
1056 format StoreMemory {
1057 0x0: sb({{ Mem.ub = Rt<7:0>; }});
1058 0x1: sh({{ Mem.uh = Rt<15:0>; }});
1059 0x3: sw({{ Mem.uw = Rt<31:0>; }});
1062 format StoreUnalignedMemory {
1063 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
1064 uint32_t mem_shift = 32 - reg_shift;
1065 mem_word = mem_word & (mask(reg_shift) << mem_shift) |
1068 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
1069 mem_word = Rt.uw << reg_shift |
1070 mem_word & (mask(reg_shift));
1074 0x7: FailUnimpl::cache();
1077 0x6: decode OPCODE_LO {
1079 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
1080 0x1: lwc1({{ Ft.uw = Mem.uw; }});
1081 0x5: ldc1({{ Ft.ud = Mem.ud; }});
1084 0x3: Prefetch::pref();
1088 0x7: decode OPCODE_LO {
1089 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
1090 {{ uint64_t tmp = write_result;
1091 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
1092 }}, mem_flags=LOCKED);
1094 format StoreMemory {
1095 0x1: swc1({{ Mem.uw = Ft.uw; }});
1096 0x5: sdc1({{ Mem.ud = Ft.ud; }});