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Merge vm1.(none):/home/stever/bk/newmem
[gem5.git] / src / arch / mips / isa / decoder.isa
1 // -*- mode:c++ -*-
2
3 // Copyright (c) 2003-2006 The Regents of The University of Michigan
4 // All rights reserved.
5 //
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
16 //
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 //
29 // Authors: Korey Sewell
30
31 ////////////////////////////////////////////////////////////////////
32 //
33 // The actual MIPS32 ISA decoder
34 // -----------------------------
35 // The following instructions are specified in the MIPS32 ISA
36 // Specification. Decoding closely follows the style specified
37 // in the MIPS32 ISA specification document starting with Table
38 // A-2 (document available @ www.mips.com)
39 //
40 decode OPCODE_HI default Unknown::unknown() {
41 //Table A-2
42 0x0: decode OPCODE_LO {
43 0x0: decode FUNCTION_HI {
44 0x0: decode FUNCTION_LO {
45 0x1: decode MOVCI {
46 format BasicOp {
47 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }});
48 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }});
49 }
50 }
51
52 format BasicOp {
53 //Table A-3 Note: "Specific encodings of the rd, rs, and
54 //rt fields are used to distinguish SLL, SSNOP, and EHB
55 //functions
56 0x0: decode RS {
57 0x0: decode RT_RD {
58 0x0: decode SA default Nop::nop(){
59 0x1: WarnUnimpl::ssnop();
60 0x3: WarnUnimpl::ehb();
61 }
62 default: sll({{ Rd = Rt.uw << SA; }});
63 }
64 }
65
66 0x2: decode RS_SRL {
67 0x0:decode SRL {
68 0: srl({{ Rd = Rt.uw >> SA; }});
69
70 //Hardcoded assuming 32-bit ISA, probably need parameter here
71 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
72 }
73 }
74
75 0x3: decode RS {
76 0x0: sra({{
77 uint32_t temp = Rt >> SA;
78 if ( (Rt & 0x80000000) > 0 ) {
79 uint32_t mask = 0x80000000;
80 for(int i=0; i < SA; i++) {
81 temp |= mask;
82 mask = mask >> 1;
83 }
84 }
85 Rd = temp;
86 }});
87 }
88
89 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
90
91 0x6: decode SRLV {
92 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
93
94 //Hardcoded assuming 32-bit ISA, probably need parameter here
95 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
96 }
97
98 0x7: srav({{
99 int shift_amt = Rs<4:0>;
100
101 uint32_t temp = Rt >> shift_amt;
102
103 if ( (Rt & 0x80000000) > 0 ) {
104 uint32_t mask = 0x80000000;
105 for(int i=0; i < shift_amt; i++) {
106 temp |= mask;
107 mask = mask >> 1;
108 }
109 }
110
111 Rd = temp;
112 }});
113 }
114 }
115
116 0x1: decode FUNCTION_LO {
117 //Table A-3 Note: "Specific encodings of the hint field are
118 //used to distinguish JR from JR.HB and JALR from JALR.HB"
119 format Jump {
120 0x0: decode HINT {
121 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
122 default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
123 }
124
125 0x1: decode HINT {
126 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall, Link
127 , ClearHazards);
128 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall,
129 Link);
130 }
131 }
132
133 format BasicOp {
134 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
135 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
136 0x4: syscall({{ xc->syscall(R2); }}, IsNonSpeculative);
137 0x7: sync({{ ; }}, IsMemBarrier);
138 }
139
140 format FailUnimpl {
141 0x5: break();
142 }
143 }
144
145 0x2: decode FUNCTION_LO {
146 format HiLoMiscOp {
147 0x0: mfhi({{ Rd = HI; }});
148 0x1: mthi({{ HI = Rs; }});
149 0x2: mflo({{ Rd = LO; }});
150 0x3: mtlo({{ LO = Rs; }});
151 }
152 }
153
154 0x3: decode FUNCTION_LO {
155 format HiLoOp {
156 0x0: mult({{ val = Rs.sd * Rt.sd; }});
157 0x1: multu({{ val = Rs.ud * Rt.ud; }});
158 }
159
160 format HiLoMiscOp {
161 0x2: div({{
162 HI = Rs.sd % Rt.sd;
163 LO = Rs.sd / Rt.sd;
164 }});
165 0x3: divu({{
166 HI = Rs.ud % Rt.ud;
167 LO = Rs.ud / Rt.ud;
168 }});
169 }
170 }
171
172 0x4: decode HINT {
173 0x0: decode FUNCTION_LO {
174 format IntOp {
175 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
176 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
177 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
178 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
179 0x4: and({{ Rd = Rs & Rt;}});
180 0x5: or({{ Rd = Rs | Rt;}});
181 0x6: xor({{ Rd = Rs ^ Rt;}});
182 0x7: nor({{ Rd = ~(Rs | Rt);}});
183 }
184 }
185 }
186
187 0x5: decode HINT {
188 0x0: decode FUNCTION_LO {
189 format IntOp{
190 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
191 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
192 }
193 }
194 }
195
196 0x6: decode FUNCTION_LO {
197 format Trap {
198 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }});
199 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
200 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
201 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
202 0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
203 0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
204 }
205 }
206 }
207
208 0x1: decode REGIMM_HI {
209 0x0: decode REGIMM_LO {
210 format Branch {
211 0x0: bltz({{ cond = (Rs.sw < 0); }});
212 0x1: bgez({{ cond = (Rs.sw >= 0); }});
213 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely);
214 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely);
215 }
216 }
217
218 0x1: decode REGIMM_LO {
219 format Trap {
220 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
221 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
222 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
223 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
224 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
225 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
226 }
227 }
228
229 0x2: decode REGIMM_LO {
230 format Branch {
231 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link);
232 0x1: decode RS {
233 0x0: bal ({{ cond = 1; }}, IsCall, Link);
234 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link);
235 }
236 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely);
237 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely);
238 }
239 }
240
241 0x3: decode REGIMM_LO {
242 format WarnUnimpl {
243 0x7: synci();
244 }
245 }
246 }
247
248 format Jump {
249 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
250 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall,
251 Link);
252 }
253
254 format Branch {
255 0x4: decode RS_RT {
256 0x0: b({{ cond = 1; }});
257 default: beq({{ cond = (Rs.sw == Rt.sw); }});
258 }
259 0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
260 0x6: blez({{ cond = (Rs.sw <= 0); }});
261 0x7: bgtz({{ cond = (Rs.sw > 0); }});
262 }
263 }
264
265 0x1: decode OPCODE_LO {
266 format IntImmOp {
267 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
268 0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
269 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
270 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
271 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
272 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
273 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
274
275 0x7: decode RS {
276 0x0: lui({{ Rt = imm << 16}});
277 }
278 }
279 }
280
281 0x2: decode OPCODE_LO {
282 //Table A-11 MIPS32 COP0 Encoding of rs Field
283 0x0: decode RS_MSB {
284 0x0: decode RS {
285 format CP0Control {
286 0x0: mfc0({{ Rt = xc->readMiscReg(RD << 5 | SEL); }});
287 0x4: mtc0({{ xc->setMiscReg(RD << 5 | SEL, Rt); }});
288 }
289
290 format MipsMT {
291 0x8: mftr();
292 0xC: mttr();
293 0xB: decode RD {
294 0x0: decode SC {
295 0x0: dvpe();
296 0x1: evpe();
297 }
298 0x1: decode SC {
299 0x0: dmt();
300 0x1: emt();
301 0xC: decode SC {
302 0x0: di();
303 0x1: ei();
304 }
305 }
306 }
307 }
308
309 format FailUnimpl {
310 0xA: rdpgpr();
311 0xE: wrpgpr();
312 }
313 }
314
315 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
316 0x1: decode FUNCTION {
317 format FailUnimpl {
318 0x01: tlbr();
319 0x02: tlbwi();
320 0x06: tlbwr();
321 0x08: tlbp();
322
323 0x18: eret();
324 0x1F: deret();
325 0x20: wait();
326 }
327 }
328 }
329
330 //Table A-13 MIPS32 COP1 Encoding of rs Field
331 0x1: decode RS_MSB {
332
333 0x0: decode RS_HI {
334 0x0: decode RS_LO {
335 format CP1Control {
336 0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }});
337
338 0x2: cfc1({{
339 switch (FS)
340 {
341 case 0:
342 Rt = FIR;
343 break;
344 case 25:
345 Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23;
346 break;
347 case 26:
348 Rt = 0 | (FCSR & 0x0003F07C);
349 break;
350 case 28:
351 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003);
352 break;
353 case 31:
354 Rt = FCSR;
355 break;
356 default:
357 panic("FP Control Value (%d) Not Valid");
358 }
359 }});
360
361 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
362
363 0x4: mtc1 ({{ Fs.uw = Rt.uw; }});
364
365 0x6: ctc1({{
366 switch (FS)
367 {
368 case 25:
369 FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25
370 | (FCSR & 0x01000000) // bit 24
371 | (FCSR & 0x004FFFFF);// bit 22...0
372 break;
373
374 case 26:
375 FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18
376 | Rt.uw<17:12> << 12 // bit 17...12
377 | (FCSR & 0x00000F80) << 7// bit 11...7
378 | Rt.uw<6:2> << 2 // bit 6...2
379 | (FCSR & 0x00000002); // bit 1...0
380 break;
381
382 case 28:
383 FCSR = 0 | (FCSR & 0xFE000000) // move 31...25
384 | Rt.uw<2:2> << 24 // bit 24
385 | (FCSR & 0x00FFF000) << 23// bit 23...12
386 | Rt.uw<11:7> << 7 // bit 24
387 | (FCSR & 0x000007E)
388 | Rt.uw<1:0>;// bit 22...0
389 break;
390
391 case 31:
392 FCSR = Rt.uw;
393 break;
394
395 default:
396 panic("FP Control Value (%d) Not Available. Ignoring Access to"
397 "Floating Control Status Register", FS);
398 }
399 }});
400
401 0x7: mthc1({{
402 uint64_t fs_hi = Rt.uw;
403 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF;
404 Fs.ud = (fs_hi << 32) | fs_lo;
405 }});
406
407 }
408 }
409
410 0x1: decode ND {
411 format Branch {
412 0x0: decode TF {
413 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
414 }});
415 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
416 }});
417 }
418 0x1: decode TF {
419 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
420 }}, Likely);
421 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
422 }}, Likely);
423 }
424 }
425 }
426 }
427
428 0x1: decode RS_HI {
429 0x2: decode RS_LO {
430 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
431 //(( single-precision floating point))
432 0x0: decode FUNCTION_HI {
433 0x0: decode FUNCTION_LO {
434 format FloatOp {
435 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}});
436 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}});
437 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}});
438 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}});
439 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}});
440 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}});
441 0x6: mov_s({{ Fd.sf = Fs.sf;}});
442 0x7: neg_s({{ Fd.sf = -Fs.sf;}});
443 }
444 }
445
446 0x1: decode FUNCTION_LO {
447 format FloatConvertOp {
448 0x0: round_l_s({{ val = Fs.sf; }}, ToLong,
449 Round);
450 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong,
451 Trunc);
452 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong,
453 Ceil);
454 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong,
455 Floor);
456 0x4: round_w_s({{ val = Fs.sf; }}, ToWord,
457 Round);
458 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord,
459 Trunc);
460 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord,
461 Ceil);
462 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord,
463 Floor);
464 }
465 }
466
467 0x2: decode FUNCTION_LO {
468 0x1: decode MOVCF {
469 format BasicOp {
470 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }});
471 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }});
472 }
473 }
474
475 format BasicOp {
476 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
477 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
478 }
479
480 format FloatOp {
481 0x5: recip_s({{ Fd = 1 / Fs; }});
482 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
483 }
484 }
485
486 0x4: decode FUNCTION_LO {
487 format FloatConvertOp {
488 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble);
489 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord);
490 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong);
491 }
492
493 0x6: FloatOp::cvt_ps_s({{
494 Fd.ud = (uint64_t) Fs.uw << 32 |
495 (uint64_t) Ft.uw;
496 }});
497 }
498
499 0x6: decode FUNCTION_LO {
500 format FloatCompareOp {
501 0x0: c_f_s({{ cond = 0; }}, SinglePrecision,
502 UnorderedFalse);
503 0x1: c_un_s({{ cond = 0; }}, SinglePrecision,
504 UnorderedTrue);
505 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }},
506 UnorderedFalse);
507 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }},
508 UnorderedTrue);
509 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }},
510 UnorderedFalse);
511 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }},
512 UnorderedTrue);
513 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }},
514 UnorderedFalse);
515 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }},
516 UnorderedTrue);
517 }
518 }
519
520 0x7: decode FUNCTION_LO {
521 format FloatCompareOp {
522 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision,
523 UnorderedFalse, QnanException);
524 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision,
525 UnorderedTrue, QnanException);
526 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}},
527 UnorderedFalse, QnanException);
528 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }},
529 UnorderedTrue, QnanException);
530 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }},
531 UnorderedFalse, QnanException);
532 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }},
533 UnorderedTrue, QnanException);
534 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }},
535 UnorderedFalse, QnanException);
536 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }},
537 UnorderedTrue, QnanException);
538 }
539 }
540 }
541
542 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
543 0x1: decode FUNCTION_HI {
544 0x0: decode FUNCTION_LO {
545 format FloatOp {
546 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }});
547 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }});
548 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }});
549 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }});
550 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }});
551 0x5: abs_d({{ Fd.df = fabs(Fs.df); }});
552 0x6: mov_d({{ Fd.df = Fs.df; }});
553 0x7: neg_d({{ Fd.df = -1 * Fs.df; }});
554 }
555 }
556
557 0x1: decode FUNCTION_LO {
558 format FloatConvertOp {
559 0x0: round_l_d({{ val = Fs.df; }}, ToLong,
560 Round);
561 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong,
562 Trunc);
563 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong,
564 Ceil);
565 0x3: floor_l_d({{ val = Fs.df; }}, ToLong,
566 Floor);
567 0x4: round_w_d({{ val = Fs.df; }}, ToWord,
568 Round);
569 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord,
570 Trunc);
571 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord,
572 Ceil);
573 0x7: floor_w_d({{ val = Fs.df; }}, ToWord,
574 Floor);
575 }
576 }
577
578 0x2: decode FUNCTION_LO {
579 0x1: decode MOVCF {
580 format BasicOp {
581 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ?
582 Fs.df : Fd.df;
583 }});
584 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ?
585 Fs.df : Fd.df;
586 }});
587 }
588 }
589
590 format BasicOp {
591 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }});
592 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }});
593 }
594
595 format FloatOp {
596 0x5: recip_d({{ Fd.df = 1 / Fs.df }});
597 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
598 }
599 }
600
601 0x4: decode FUNCTION_LO {
602 format FloatConvertOp {
603 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
604 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
605 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
606 }
607 }
608
609 0x6: decode FUNCTION_LO {
610 format FloatCompareOp {
611 0x0: c_f_d({{ cond = 0; }}, DoublePrecision,
612 UnorderedFalse);
613 0x1: c_un_d({{ cond = 0; }}, DoublePrecision,
614 UnorderedTrue);
615 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }},
616 UnorderedFalse);
617 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }},
618 UnorderedTrue);
619 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }},
620 UnorderedFalse);
621 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }},
622 UnorderedTrue);
623 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }},
624 UnorderedFalse);
625 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }},
626 UnorderedTrue);
627 }
628 }
629
630 0x7: decode FUNCTION_LO {
631 format FloatCompareOp {
632 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision,
633 UnorderedFalse, QnanException);
634 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision,
635 UnorderedTrue, QnanException);
636 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }},
637 UnorderedFalse, QnanException);
638 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }},
639 UnorderedTrue, QnanException);
640 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }},
641 UnorderedFalse, QnanException);
642 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }},
643 UnorderedTrue, QnanException);
644 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }},
645 UnorderedFalse, QnanException);
646 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }},
647 UnorderedTrue, QnanException);
648 }
649 }
650 }
651
652 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
653 0x4: decode FUNCTION {
654 format FloatConvertOp {
655 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
656 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
657 0x26: FailUnimpl::cvt_ps_w();
658 }
659 }
660
661 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
662 //Note: "1. Format type L is legal only if 64-bit floating point operations
663 //are enabled."
664 0x5: decode FUNCTION_HI {
665 format FloatConvertOp {
666 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
667 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
668 0x26: FailUnimpl::cvt_ps_l();
669 }
670 }
671
672 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
673 //Note: "1. Format type PS is legal only if 64-bit floating point operations
674 //are enabled. "
675 0x6: decode FUNCTION_HI {
676 0x0: decode FUNCTION_LO {
677 format Float64Op {
678 0x0: add_ps({{
679 Fd1.sf = Fs1.sf + Ft2.sf;
680 Fd2.sf = Fs2.sf + Ft2.sf;
681 }});
682 0x1: sub_ps({{
683 Fd1.sf = Fs1.sf - Ft2.sf;
684 Fd2.sf = Fs2.sf - Ft2.sf;
685 }});
686 0x2: mul_ps({{
687 Fd1.sf = Fs1.sf * Ft2.sf;
688 Fd2.sf = Fs2.sf * Ft2.sf;
689 }});
690 0x5: abs_ps({{
691 Fd1.sf = fabs(Fs1.sf);
692 Fd2.sf = fabs(Fs2.sf);
693 }});
694 0x6: mov_ps({{
695 Fd1.sf = Fs1.sf;
696 Fd2.sf = Fs2.sf;
697 }});
698 0x7: neg_ps({{
699 Fd1.sf = -(Fs1.sf);
700 Fd2.sf = -(Fs2.sf);
701 }});
702 }
703 }
704
705 0x2: decode FUNCTION_LO {
706 0x1: decode MOVCF {
707 format Float64Op {
708 0x0: movf_ps({{
709 Fd1 = (getCondCode(FCSR, CC) == 0) ?
710 Fs1 : Fd1;
711 Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
712 Fs2 : Fd2;
713 }});
714 0x1: movt_ps({{
715 Fd2 = (getCondCode(FCSR, CC) == 1) ?
716 Fs1 : Fd1;
717 Fd2 = (getCondCode(FCSR, CC+1) == 1) ?
718 Fs2 : Fd2;
719 }});
720 }
721 }
722
723 format Float64Op {
724 0x2: movz_ps({{
725 Fd1 = (getCondCode(FCSR, CC) == 0) ?
726 Fs1 : Fd1;
727 Fd2 = (getCondCode(FCSR, CC) == 0) ?
728 Fs2 : Fd2;
729 }});
730 0x3: movn_ps({{
731 Fd1 = (getCondCode(FCSR, CC) == 1) ?
732 Fs1 : Fd1;
733 Fd2 = (getCondCode(FCSR, CC) == 1) ?
734 Fs2 : Fd2;
735 }});
736 }
737
738 }
739
740 0x4: decode FUNCTION_LO {
741 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
742 }
743
744 0x5: decode FUNCTION_LO {
745 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }});
746
747 format Float64Op {
748 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
749 Ft1.uw;
750 }});
751 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
752 Ft2.uw;
753 }});
754 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
755 Ft1.uw;
756 }});
757 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
758 Ft2.uw;
759 }});
760 }
761 }
762
763 0x6: decode FUNCTION_LO {
764 format FloatPSCompareOp {
765 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
766 UnorderedFalse);
767 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
768 UnorderedTrue);
769 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
770 {{ cond2 = (Fs2.sf == Ft2.sf); }},
771 UnorderedFalse);
772 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
773 {{ cond2 = (Fs2.sf == Ft2.sf); }},
774 UnorderedTrue);
775 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
776 {{ cond2 = (Fs2.sf < Ft2.sf); }},
777 UnorderedFalse);
778 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }},
779 {{ cond2 = (Fs2.sf < Ft2.sf); }},
780 UnorderedTrue);
781 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }},
782 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
783 UnorderedFalse);
784 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
785 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
786 UnorderedTrue);
787 }
788 }
789
790 0x7: decode FUNCTION_LO {
791 format FloatPSCompareOp {
792 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
793 UnorderedFalse, QnanException);
794 0x1: c_ngle_ps({{ cond1 = 0; }},
795 {{ cond2 = 0; }},
796 UnorderedTrue, QnanException);
797 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
798 {{ cond2 = (Fs2.sf == Ft2.sf); }},
799 UnorderedFalse, QnanException);
800 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
801 {{ cond2 = (Fs2.sf == Ft2.sf); }},
802 UnorderedTrue, QnanException);
803 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
804 {{ cond2 = (Fs2.sf < Ft2.sf); }},
805 UnorderedFalse, QnanException);
806 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
807 {{ cond2 = (Fs2.sf < Ft2.sf); }},
808 UnorderedTrue, QnanException);
809 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
810 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
811 UnorderedFalse, QnanException);
812 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
813 {{ cond2 = (Fs2.sf <= Ft2.sf); }},
814 UnorderedTrue, QnanException);
815 }
816 }
817 }
818 }
819 }
820 }
821
822 //Table A-19 MIPS32 COP2 Encoding of rs Field
823 0x2: decode RS_MSB {
824 format FailUnimpl {
825 0x0: decode RS_HI {
826 0x0: decode RS_LO {
827 0x0: mfc2();
828 0x2: cfc2();
829 0x3: mfhc2();
830 0x4: mtc2();
831 0x6: ctc2();
832 0x7: mftc2();
833 }
834
835 0x1: decode ND {
836 0x0: decode TF {
837 0x0: bc2f();
838 0x1: bc2t();
839 }
840
841 0x1: decode TF {
842 0x0: bc2fl();
843 0x1: bc2tl();
844 }
845 }
846 }
847 }
848 }
849
850 //Table A-20 MIPS64 COP1X Encoding of Function Field 1
851 //Note: "COP1X instructions are legal only if 64-bit floating point
852 //operations are enabled."
853 0x3: decode FUNCTION_HI {
854 0x0: decode FUNCTION_LO {
855 format LoadIndexedMemory {
856 0x0: lwxc1({{ Ft.uw = Mem.uw;}});
857 0x1: ldxc1({{ Ft.ud = Mem.ud;}});
858 0x5: luxc1({{ Ft.uw = Mem.ud;}});
859 }
860 }
861
862 0x1: decode FUNCTION_LO {
863 format StoreIndexedMemory {
864 0x0: swxc1({{ Mem.uw = Ft.uw;}});
865 0x1: sdxc1({{ Mem.ud = Ft.ud;}});
866 0x5: suxc1({{ Mem.ud = Ft.ud;}});
867 }
868
869 0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
870 }
871
872 0x3: decode FUNCTION_LO {
873 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) {
874 Fd.ud = Fs.ud;
875 } else if (Rs<2:0> == 4) {
876 #if BYTE_ORDER == BIG_ENDIAN
877 Fd.ud = Fs.ud<31:0> << 32 |
878 Ft.ud<63:32>;
879 #elif BYTE_ORDER == LITTLE_ENDIAN
880 Fd.ud = Ft.ud<31:0> << 32 |
881 Fs.ud<63:32>;
882 #endif
883 } else {
884 Fd.ud = Fd.ud;
885 }
886 }});
887 }
888
889 format FloatAccOp {
890 0x4: decode FUNCTION_LO {
891 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }});
892 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }});
893 0x6: madd_ps({{
894 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df;
895 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df;
896 }});
897 }
898
899 0x5: decode FUNCTION_LO {
900 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }});
901 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }});
902 0x6: msub_ps({{
903 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df;
904 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df;
905 }});
906 }
907
908 0x6: decode FUNCTION_LO {
909 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
910 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }});
911 0x6: nmadd_ps({{
912 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df);
913 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df);
914 }});
915 }
916
917 0x7: decode FUNCTION_LO {
918 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
919 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }});
920 0x6: nmsub_ps({{
921 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df);
922 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df);
923 }});
924 }
925
926 }
927 }
928
929 format Branch {
930 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely);
931 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely);
932 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely);
933 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely);
934 }
935 }
936
937 0x3: decode OPCODE_LO {
938 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
939 0x4: decode FUNCTION_HI {
940 0x0: decode FUNCTION_LO {
941 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
942 Rd.sw = temp1<31:0>
943 }});
944
945 format HiLoOp {
946 0x0: madd({{ val = ((int64_t) HI << 32 | LO) +
947 (Rs.sd * Rt.sd);
948 }});
949 0x1: maddu({{ val = ((uint64_t) HI << 32 | LO) +
950 (Rs.ud * Rt.ud);
951 }});
952 0x4: msub({{ val = ((int64_t) HI << 32 | LO) -
953 (Rs.sd * Rt.sd);
954 }});
955 0x5: msubu({{ val = ((uint64_t) HI << 32 | LO) -
956 (Rs.ud * Rt.ud);
957 }});
958 }
959 }
960
961 0x4: decode FUNCTION_LO {
962 format BasicOp {
963 0x0: clz({{ int cnt = 32;
964 for (int idx = 31; idx >= 0; idx--) {
965 if( Rs<idx:idx> == 1) {
966 cnt = 31 - idx;
967 break;
968 }
969 }
970 Rd.uw = cnt;
971 }});
972 0x1: clo({{ int cnt = 32;
973 for (int idx = 31; idx >= 0; idx--) {
974 if( Rs<idx:idx> == 0) {
975 cnt = 31 - idx;
976 break;
977 }
978 }
979 Rd.uw = cnt;
980 }});
981 }
982 }
983
984 0x7: decode FUNCTION_LO {
985 0x7: FailUnimpl::sdbbp();
986 }
987 }
988
989 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2
990 //of the Architecture
991 0x7: decode FUNCTION_HI {
992 0x0: decode FUNCTION_LO {
993 format BasicOp {
994 0x1: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }});
995 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) |
996 bits(Rs.uw, MSB-LSB, 0) << LSB |
997 bits(Rt.uw, LSB-1, 0);
998 }});
999 }
1000 }
1001
1002 0x1: decode FUNCTION_LO {
1003 format MipsMT {
1004 0x0: fork();
1005 0x1: yield();
1006 }
1007 }
1008
1009 //Table A-10 MIPS32 BSHFL Encoding of sa Field
1010 0x4: decode SA {
1011 format BasicOp {
1012 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 |
1013 Rt.uw<31:24> << 16 |
1014 Rt.uw<7:0> << 8 |
1015 Rt.uw<15:8>;
1016 }});
1017 0x10: seb({{ Rd.sw = Rt.sw<7:0>}});
1018 0x18: seh({{ Rd.sw = Rt.sw<15:0>}});
1019 }
1020 }
1021
1022 0x6: decode FUNCTION_LO {
1023 0x7: FailUnimpl::rdhwr();
1024 }
1025 }
1026 }
1027
1028 0x4: decode OPCODE_LO {
1029 format LoadMemory {
1030 0x0: lb({{ Rt.sw = Mem.sb; }});
1031 0x1: lh({{ Rt.sw = Mem.sh; }});
1032 0x3: lw({{ Rt.sw = Mem.sw; }});
1033 0x4: lbu({{ Rt.uw = Mem.ub; }});
1034 0x5: lhu({{ Rt.uw = Mem.uh; }});
1035 }
1036
1037 format LoadUnalignedMemory {
1038 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
1039 Rt.uw = mem_word << mem_shift |
1040 Rt.uw & mask(mem_shift);
1041 }});
1042 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
1043 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
1044 mem_word >> mem_shift;
1045 }});
1046 }
1047 }
1048
1049 0x5: decode OPCODE_LO {
1050 format StoreMemory {
1051 0x0: sb({{ Mem.ub = Rt<7:0>; }});
1052 0x1: sh({{ Mem.uh = Rt<15:0>; }});
1053 0x3: sw({{ Mem.uw = Rt<31:0>; }});
1054 }
1055
1056 format StoreUnalignedMemory {
1057 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
1058 uint32_t mem_shift = 32 - reg_shift;
1059 mem_word = mem_word & (mask(reg_shift) << mem_shift) |
1060 Rt.uw >> reg_shift;
1061 }});
1062 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
1063 mem_word = Rt.uw << reg_shift |
1064 mem_word & (mask(reg_shift));
1065 }});
1066 }
1067
1068 0x7: FailUnimpl::cache();
1069 }
1070
1071 0x6: decode OPCODE_LO {
1072 format LoadMemory {
1073 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
1074 0x1: lwc1({{ Ft.uw = Mem.uw; }});
1075 0x5: ldc1({{ Ft.ud = Mem.ud; }});
1076 }
1077
1078 0x3: Prefetch::pref();
1079 }
1080
1081
1082 0x7: decode OPCODE_LO {
1083 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
1084 {{ uint64_t tmp = write_result;
1085 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
1086 }}, mem_flags=LOCKED);
1087
1088 format StoreMemory {
1089 0x1: swc1({{ Mem.uw = Ft.uw; }});
1090 0x5: sdc1({{ Mem.ud = Ft.ud; }});
1091 }
1092 }
1093 }
1094
1095