3 // Copyright (c) 2007 MIPS Technologies, Inc.
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Korey Sewell
33 ////////////////////////////////////////////////////////////////////
35 // The actual MIPS32 ISA decoder
36 // -----------------------------
37 // The following instructions are specified in the MIPS32 ISA
38 // Specification. Decoding closely follows the style specified
39 // in the MIPS32 ISA specification document starting with Table
40 // A-2 (document available @ http://www.mips.com)
42 decode OPCODE_HI default Unknown::unknown() {
44 0x0: decode OPCODE_LO {
45 0x0: decode FUNCTION_HI {
46 0x0: decode FUNCTION_LO {
50 Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs;
53 Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs;
59 //Table A-3 Note: "Specific encodings of the rd, rs, and
60 //rt fields are used to distinguish SLL, SSNOP, and EHB
64 0x0: decode SA default Nop::nop() {
68 default: sll({{ Rd = Rt_uw << SA; }});
74 0: srl({{ Rd = Rt_uw >> SA; }});
76 //Hardcoded assuming 32-bit ISA,
77 //probably need parameter here
79 Rd = (Rt_uw << (32 - SA)) | (Rt_uw >> SA);
86 uint32_t temp = Rt >> SA;
87 if ( (Rt & 0x80000000) > 0 ) {
88 uint32_t mask = 0x80000000;
89 for(int i=0; i < SA; i++) {
98 0x4: sllv({{ Rd = Rt_uw << Rs<4:0>; }});
101 0: srlv({{ Rd = Rt_uw >> Rs<4:0>; }});
103 //Hardcoded assuming 32-bit ISA,
104 //probably need parameter here
106 Rd = (Rt_uw << (32 - Rs<4:0>)) |
112 int shift_amt = Rs<4:0>;
114 uint32_t temp = Rt >> shift_amt;
116 if ((Rt & 0x80000000) > 0) {
117 uint32_t mask = 0x80000000;
118 for (int i = 0; i < shift_amt; i++) {
128 0x1: decode FUNCTION_LO {
129 //Table A-3 Note: "Specific encodings of the hint field are
130 //used to distinguish JR from JR.HB and JALR from JALR.HB"
134 Config1Reg config1 = Config1;
135 if (config1.ca == 0) {
138 panic("MIPS16e not supported\n");
140 }}, IsReturn, ClearHazards);
142 Config1Reg config1 = Config1;
143 if (config1.ca == 0) {
146 panic("MIPS16e not supported\n");
155 }}, IsCall, ClearHazards);
164 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
165 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
166 0x4: decode FULL_SYSTEM {
167 0: syscall_se({{ xc->syscall(R2); }},
168 IsSerializeAfter, IsNonSpeculative);
169 default: syscall({{ fault = new SystemCallFault(); }});
171 0x7: sync({{ ; }}, IsMemBarrier);
172 0x5: break({{fault = new BreakpointFault();}});
177 0x2: decode FUNCTION_LO {
178 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }},
179 IntMultOp, IsIprAccess);
180 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
181 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }},
182 IntMultOp, IsIprAccess);
183 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
186 0x3: decode FUNCTION_LO {
187 format HiLoRdSelValOp {
188 0x0: mult({{ val = Rs_sd * Rt_sd; }}, IntMultOp);
189 0x1: multu({{ val = Rs_ud * Rt_ud; }}, IntMultOp);
210 0x0: decode FUNCTION_LO {
214 Rd = result = Rs + Rt;
216 findOverflow(32, result, Rs, Rt)) {
217 fault = new IntegerOverflowFault();
220 0x1: addu({{ Rd_sw = Rs_sw + Rt_sw;}});
223 Rd = result = Rs - Rt;
225 findOverflow(32, result, Rs, ~Rt)) {
226 fault = new IntegerOverflowFault();
229 0x3: subu({{ Rd_sw = Rs_sw - Rt_sw; }});
230 0x4: and({{ Rd = Rs & Rt; }});
231 0x5: or({{ Rd = Rs | Rt; }});
232 0x6: xor({{ Rd = Rs ^ Rt; }});
233 0x7: nor({{ Rd = ~(Rs | Rt); }});
239 0x0: decode FUNCTION_LO {
241 0x2: slt({{ Rd_sw = (Rs_sw < Rt_sw) ? 1 : 0 }});
242 0x3: sltu({{ Rd_uw = (Rs_uw < Rt_uw) ? 1 : 0 }});
247 0x6: decode FUNCTION_LO {
249 0x0: tge({{ cond = (Rs_sw >= Rt_sw); }});
250 0x1: tgeu({{ cond = (Rs_uw >= Rt_uw); }});
251 0x2: tlt({{ cond = (Rs_sw < Rt_sw); }});
252 0x3: tltu({{ cond = (Rs_uw < Rt_uw); }});
253 0x4: teq({{ cond = (Rs_sw == Rt_sw); }});
254 0x6: tne({{ cond = (Rs_sw != Rt_sw); }});
259 0x1: decode REGIMM_HI {
260 0x0: decode REGIMM_LO {
262 0x0: bltz({{ cond = (Rs_sw < 0); }});
263 0x1: bgez({{ cond = (Rs_sw >= 0); }});
264 0x2: bltzl({{ cond = (Rs_sw < 0); }}, Likely);
265 0x3: bgezl({{ cond = (Rs_sw >= 0); }}, Likely);
269 0x1: decode REGIMM_LO {
271 0x0: tgei( {{ cond = (Rs_sw >= (int16_t)INTIMM); }});
273 cond = (Rs_uw >= (uint32_t)(int32_t)(int16_t)INTIMM);
275 0x2: tlti( {{ cond = (Rs_sw < (int16_t)INTIMM); }});
277 cond = (Rs_uw < (uint32_t)(int32_t)(int16_t)INTIMM);
279 0x4: teqi( {{ cond = (Rs_sw == (int16_t)INTIMM); }});
280 0x6: tnei( {{ cond = (Rs_sw != (int16_t)INTIMM); }});
284 0x2: decode REGIMM_LO {
286 0x0: bltzal({{ cond = (Rs_sw < 0); }}, Link);
288 0x0: bal ({{ cond = 1; }}, IsCall, Link);
289 default: bgezal({{ cond = (Rs_sw >= 0); }}, Link);
291 0x2: bltzall({{ cond = (Rs_sw < 0); }}, Link, Likely);
292 0x3: bgezall({{ cond = (Rs_sw >= 0); }}, Link, Likely);
296 0x3: decode REGIMM_LO {
297 // from Table 5-4 MIPS32 REGIMM Encoding of rt Field
299 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }});
307 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }});
308 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},
314 0x0: b({{ cond = 1; }});
315 default: beq({{ cond = (Rs_sw == Rt_sw); }});
317 0x5: bne({{ cond = (Rs_sw != Rt_sw); }});
318 0x6: blez({{ cond = (Rs_sw <= 0); }});
319 0x7: bgtz({{ cond = (Rs_sw > 0); }});
323 0x1: decode OPCODE_LO {
327 Rt = result = Rs + imm;
329 findOverflow(32, result, Rs, imm)) {
330 fault = new IntegerOverflowFault();
333 0x1: addiu({{ Rt_sw = Rs_sw + imm; }});
334 0x2: slti({{ Rt_sw = (Rs_sw < imm) ? 1 : 0 }});
335 0x3: sltiu({{ Rt_uw = (Rs_uw < (uint32_t)sextImm) ? 1 : 0;}});
336 0x4: andi({{ Rt_sw = Rs_sw & zextImm; }});
337 0x5: ori({{ Rt_sw = Rs_sw | zextImm; }});
338 0x6: xori({{ Rt_sw = Rs_sw ^ zextImm; }});
341 0x0: lui({{ Rt = imm << 16; }});
346 0x2: decode OPCODE_LO {
347 //Table A-11 MIPS32 COP0 Encoding of rs Field
352 Config3Reg config3 = Config3;
353 PageGrainReg pageGrain = PageGrain;
355 /* Hack for PageMask */
358 if (config3.sp == 0 || pageGrain.esp == 0)
364 CauseReg cause = Cause;
365 IntCtlReg intCtl = IntCtl;
370 int offset = 10; // corresponding to cause.ip0
371 offset += intCtl.ipti - 2;
372 replaceBits(cause, offset, offset, 0);
384 // Decode MIPS MT MFTR instruction into sub-instructions
387 data = xc->readRegOtherThread((RT << 3 | SEL) +
392 data = xc->readRegOtherThread(RT);
395 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }});
396 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }});
397 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }});
398 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }});
399 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }});
400 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }});
401 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }});
402 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }});
403 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }});
404 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }});
405 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }});
406 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }});
407 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }});
408 default: CP0Unimpl::unknown();
411 0x0: mftc1({{ data = xc->readRegOtherThread(RT +
414 0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
419 uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
423 data = xc->readRegOtherThread(FLOATREG_FIR +
427 data = (fcsr_val & 0xFE000000 >> 24) |
428 (fcsr_val & 0x00800000 >> 23);
431 data = fcsr_val & 0x0003F07C;
434 data = (fcsr_val & 0x00000F80) |
435 (fcsr_val & 0x01000000 >> 21) |
436 (fcsr_val & 0x00000003);
442 fatal("FP Control Value (%d) Not Valid");
445 default: CP0Unimpl::unknown();
451 // Decode MIPS MT MTTR instruction into sub-instructions
453 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
457 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
459 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt);
461 0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0,
464 0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0,
467 0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1,
470 0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1,
473 0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1,
476 0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2,
479 0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2,
482 0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2,
485 0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3,
488 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3,
491 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt);
493 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }});
494 default: CP0Unimpl::unknown();
498 uint64_t data = xc->readRegOtherThread(RD +
500 data = insertBits(data, MT_H ? 63 : 31,
502 xc->setRegOtherThread(RD + FP_Base_DepTag,
509 data = (Rt_uw<7:1> << 25) | // move 31-25
510 (FCSR & 0x01000000) | // bit 24
511 (FCSR & 0x004FFFFF); // bit 22-0
514 data = (FCSR & 0xFFFC0000) | // move 31-18
515 Rt_uw<17:12> << 12 | // bit 17-12
516 (FCSR & 0x00000F80) << 7 | // bit 11-7
517 Rt_uw<6:2> << 2 | // bit 6-2
518 (FCSR & 0x00000002); // bit 1...0
521 data = (FCSR & 0xFE000000) | // move 31-25
522 Rt_uw<2:2> << 24 | // bit 24
523 (FCSR & 0x00FFF000) << 23 | // bit 23-12
524 Rt_uw<11:7> << 7 | // bit 24
526 Rt_uw<1:0>; // bit 22-0
532 panic("FP Control Value (%d) "
533 "Not Available. Ignoring "
534 "Access to Floating Control "
535 "S""tatus Register", FS);
537 xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data);
539 default: CP0Unimpl::unknown();
549 MVPControlReg mvpControl = MVPControl;
550 VPEConf0Reg vpeConf0 = VPEConf0;
552 if (vpeConf0.mvp == 1)
554 MVPControl = mvpControl;
557 MVPControlReg mvpControl = MVPControl;
558 VPEConf0Reg vpeConf0 = VPEConf0;
560 if (vpeConf0.mvp == 1)
562 MVPControl = mvpControl;
564 default:CP0Unimpl::unknown();
566 default:CP0Unimpl::unknown();
568 default:CP0Unimpl::unknown();
574 VPEControlReg vpeControl = VPEControl;
577 VPEControl = vpeControl;
580 VPEControlReg vpeControl = VPEControl;
583 VPEControl = vpeControl;
585 default:CP0Unimpl::unknown();
587 default:CP0Unimpl::unknown();
589 default:CP0Unimpl::unknown();
594 0x0: CP0Control::di({{
595 StatusReg status = Status;
596 ConfigReg config = Config;
597 // Rev 2.0 or beyond?
598 if (config.ar >= 1) {
602 // Enable this else branch once we
603 // actually set values for Config on init
604 fault = new ReservedInstructionFault();
608 0x1: CP0Control::ei({{
609 StatusReg status = Status;
610 ConfigReg config = Config;
611 if (config.ar >= 1) {
615 fault = new ReservedInstructionFault();
618 default:CP0Unimpl::unknown();
621 default: CP0Unimpl::unknown();
625 ConfigReg config = Config;
626 if (config.ar >= 1) {
627 // Rev 2 of the architecture
628 panic("Shadow Sets Not Fully Implemented.\n");
630 fault = new ReservedInstructionFault();
634 ConfigReg config = Config;
635 if (config.ar >= 1) {
636 // Rev 2 of the architecture
637 panic("Shadow Sets Not Fully Implemented.\n");
639 fault = new ReservedInstructionFault();
645 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
646 0x1: decode FUNCTION {
649 StatusReg status = Status;
650 ConfigReg config = Config;
651 SRSCtlReg srsCtl = SRSCtl;
652 DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
653 if (status.erl == 1) {
656 // Need to adjust NNPC, otherwise things break
657 NNPC = ErrorEPC + sizeof(MachInst);
660 // Need to adjust NNPC, otherwise things break
661 NNPC = EPC + sizeof(MachInst);
666 srsCtl.css = srsCtl.pss;
667 //xc->setShadowSet(srsCtl.pss);
673 }}, IsReturn, IsSerializing, IsERET);
676 DebugReg debug = Debug;
686 }}, IsReturn, IsSerializing, IsERET);
690 MipsISA::PTE *PTEntry =
691 xc->tcBase()->getITBPtr()->
692 getEntry(Index & 0x7FFFFFFF);
693 if (PTEntry == NULL) {
694 fatal("Invalid PTE Entry received on "
695 "a TLBR instruction\n");
698 // If 1KB pages are not enabled, a read of PageMask
699 // must return 0b00 in bits 12, 11
700 PageMask = (PTEntry->Mask << 11);
702 EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid));
703 /* Setup Entry Lo0 */
704 EntryLo0 = ((PTEntry->PFN0 << 6) |
709 /* Setup Entry Lo1 */
710 EntryLo1 = ((PTEntry->PFN1 << 6) |
715 }}); // Need to hook up to TLB
719 MipsISA::PTE newEntry;
721 newEntry.Mask = (Addr)(PageMask >> 11);
722 newEntry.VPN = (Addr)(EntryHi >> 11);
723 /* PageGrain _ ESP Config3 _ SP */
724 if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) {
725 // If 1KB pages are *NOT* enabled, lowest bits of
726 // the mask are 0b11 for TLB writes
727 newEntry.Mask |= 0x3;
728 // Reset bits 0 and 1 if 1KB pages are not enabled
729 newEntry.VPN &= 0xFFFFFFFC;
731 newEntry.asid = (uint8_t)(EntryHi & 0xFF);
733 newEntry.PFN0 = (Addr)(EntryLo0 >> 6);
734 newEntry.PFN1 = (Addr)(EntryLo1 >> 6);
735 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
736 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
737 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
738 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
739 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
740 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
741 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
742 /* Now, compute the AddrShiftAmount and OffsetMask -
744 /* Addr Shift Amount for 1KB or larger pages */
745 if ((newEntry.Mask & 0xFFFF) == 3) {
746 newEntry.AddrShiftAmount = 12;
747 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) {
748 newEntry.AddrShiftAmount = 10;
749 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) {
750 newEntry.AddrShiftAmount = 14;
751 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) {
752 newEntry.AddrShiftAmount = 16;
753 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) {
754 newEntry.AddrShiftAmount = 18;
755 } else if ((newEntry.Mask & 0xFF00) == 0x0300) {
756 newEntry.AddrShiftAmount = 20;
757 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) {
758 newEntry.AddrShiftAmount = 22;
759 } else if ((newEntry.Mask & 0xF000) == 0x3000) {
760 newEntry.AddrShiftAmount = 24;
761 } else if ((newEntry.Mask & 0xC000) == 0xC000) {
762 newEntry.AddrShiftAmount = 26;
763 } else if ((newEntry.Mask & 0x30000) == 0x30000) {
764 newEntry.AddrShiftAmount = 28;
766 fatal("Invalid Mask Pattern Detected!\n");
768 newEntry.OffsetMask =
769 (1 << newEntry.AddrShiftAmount) - 1;
771 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr();
772 Config3Reg config3 = Config3;
773 PageGrainReg pageGrain = PageGrain;
775 if (bits(config3, config3.sp) == 1 &&
776 bits(pageGrain, pageGrain.esp) == 1) {
779 Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP);
783 MipsISA::PTE newEntry;
785 newEntry.Mask = (Addr)(PageMask >> 11);
786 newEntry.VPN = (Addr)(EntryHi >> 11);
787 /* PageGrain _ ESP Config3 _ SP */
788 if (bits(PageGrain, 28) == 0 ||
789 bits(Config3, 4) == 0) {
790 // If 1KB pages are *NOT* enabled, lowest bits of
791 // the mask are 0b11 for TLB writes
792 newEntry.Mask |= 0x3;
793 // Reset bits 0 and 1 if 1KB pages are not enabled
794 newEntry.VPN &= 0xFFFFFFFC;
796 newEntry.asid = (uint8_t)(EntryHi & 0xFF);
798 newEntry.PFN0 = (Addr)(EntryLo0 >> 6);
799 newEntry.PFN1 = (Addr)(EntryLo1 >> 6);
800 newEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
801 newEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
802 newEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
803 newEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
804 newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
805 newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
806 newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
807 /* Now, compute the AddrShiftAmount and OffsetMask -
809 /* Addr Shift Amount for 1KB or larger pages */
810 if ((newEntry.Mask & 0xFFFF) == 3){
811 newEntry.AddrShiftAmount = 12;
812 } else if ((newEntry.Mask & 0xFFFF) == 0x0000) {
813 newEntry.AddrShiftAmount = 10;
814 } else if ((newEntry.Mask & 0xFFFC) == 0x000C) {
815 newEntry.AddrShiftAmount = 14;
816 } else if ((newEntry.Mask & 0xFFF0) == 0x0030) {
817 newEntry.AddrShiftAmount = 16;
818 } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) {
819 newEntry.AddrShiftAmount = 18;
820 } else if ((newEntry.Mask & 0xFF00) == 0x0300) {
821 newEntry.AddrShiftAmount = 20;
822 } else if ((newEntry.Mask & 0xFC00) == 0x0C00) {
823 newEntry.AddrShiftAmount = 22;
824 } else if ((newEntry.Mask & 0xF000) == 0x3000) {
825 newEntry.AddrShiftAmount = 24;
826 } else if ((newEntry.Mask & 0xC000) == 0xC000) {
827 newEntry.AddrShiftAmount = 26;
828 } else if ((newEntry.Mask & 0x30000) == 0x30000) {
829 newEntry.AddrShiftAmount = 28;
831 fatal("Invalid Mask Pattern Detected!\n");
833 newEntry.OffsetMask =
834 (1 << newEntry.AddrShiftAmount) - 1;
836 MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr();
837 Config3Reg config3 = Config3;
838 PageGrainReg pageGrain = PageGrain;
840 if (bits(config3, config3.sp) == 1 &&
841 bits(pageGrain, pageGrain.esp) == 1) {
844 Ptr->insertAt(newEntry, Random, SP);
848 Config3Reg config3 = Config3;
849 PageGrainReg pageGrain = PageGrain;
850 EntryHiReg entryHi = EntryHi;
853 if (pageGrain.esp == 1 && config3.sp ==1) {
856 // Mask off lower 2 bits
857 vpn = ((EntryHi >> 11) & 0xFFFFFFFC);
859 tlbIndex = xc->tcBase()->getITBPtr()->
860 probeEntry(vpn, entryHi.asid);
861 // Check TLB for entry matching EntryHi
862 if (tlbIndex != -1) {
865 // else, set Index = 1 << 31
873 default: CP0Unimpl::unknown();
877 //Table A-13 MIPS32 COP1 Encoding of rs Field
882 0x0: mfc1 ({{ Rt_uw = Fs_uw; }});
890 Rt = (FCSR & 0xFE000000) >> 24 |
891 (FCSR & 0x00800000) >> 23;
894 Rt = (FCSR & 0x0003F07C);
897 Rt = (FCSR & 0x00000F80) |
898 (FCSR & 0x01000000) >> 21 |
905 warn("FP Control Value (%d) Not Valid");
909 0x3: mfhc1({{ Rt_uw = Fs_ud<63:32>; }});
911 0x4: mtc1({{ Fs_uw = Rt_uw; }});
916 FCSR = (Rt_uw<7:1> << 25) | // move 31-25
917 (FCSR & 0x01000000) | // bit 24
918 (FCSR & 0x004FFFFF); // bit 22-0
921 FCSR = (FCSR & 0xFFFC0000) | // move 31-18
922 Rt_uw<17:12> << 12 | // bit 17-12
923 (FCSR & 0x00000F80) << 7 | // bit 11-7
924 Rt_uw<6:2> << 2 | // bit 6-2
925 (FCSR & 0x00000002); // bit 1-0
928 FCSR = (FCSR & 0xFE000000) | // move 31-25
929 Rt_uw<2:2> << 24 | // bit 24
930 (FCSR & 0x00FFF000) << 23 | // bit 23-12
931 Rt_uw<11:7> << 7 | // bit 24
933 Rt_uw<1:0>; // bit 22-0
940 panic("FP Control Value (%d) "
941 "Not Available. Ignoring Access "
942 "to Floating Control Status "
948 uint64_t fs_hi = Rt_uw;
949 uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF;
950 Fs_ud = (fs_hi << 32) | fs_lo;
965 cond = getCondCode(FCSR, BRANCH_CC) == 0;
968 cond = getCondCode(FCSR, BRANCH_CC) == 1;
973 cond = getCondCode(FCSR, BRANCH_CC) == 0;
976 cond = getCondCode(FCSR, BRANCH_CC) == 1;
991 //Table A-14 MIPS32 COP1 Encoding of Function Field When
992 //rs=S (( single-precision floating point))
993 0x0: decode FUNCTION_HI {
994 0x0: decode FUNCTION_LO {
996 0x0: add_s({{ Fd_sf = Fs_sf + Ft_sf; }});
997 0x1: sub_s({{ Fd_sf = Fs_sf - Ft_sf; }});
998 0x2: mul_s({{ Fd_sf = Fs_sf * Ft_sf; }});
999 0x3: div_s({{ Fd_sf = Fs_sf / Ft_sf; }});
1000 0x4: sqrt_s({{ Fd_sf = sqrt(Fs_sf); }});
1001 0x5: abs_s({{ Fd_sf = fabs(Fs_sf); }});
1002 0x7: neg_s({{ Fd_sf = -Fs_sf; }});
1004 0x6: BasicOp::mov_s({{ Fd_sf = Fs_sf; }});
1006 0x1: decode FUNCTION_LO {
1007 format FloatConvertOp {
1008 0x0: round_l_s({{ val = Fs_sf; }},
1010 0x1: trunc_l_s({{ val = Fs_sf; }},
1012 0x2: ceil_l_s({{ val = Fs_sf;}},
1014 0x3: floor_l_s({{ val = Fs_sf; }},
1016 0x4: round_w_s({{ val = Fs_sf; }},
1018 0x5: trunc_w_s({{ val = Fs_sf; }},
1020 0x6: ceil_w_s({{ val = Fs_sf; }},
1022 0x7: floor_w_s({{ val = Fs_sf; }},
1027 0x2: decode FUNCTION_LO {
1031 Fd = (getCondCode(FCSR,CC) == 0) ?
1035 Fd = (getCondCode(FCSR,CC) == 1) ?
1042 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
1043 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
1047 0x5: recip_s({{ Fd = 1 / Fs; }});
1048 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }});
1054 0x3: CP1Unimpl::unknown();
1056 0x4: decode FUNCTION_LO {
1057 format FloatConvertOp {
1058 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble);
1059 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord);
1060 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong);
1063 0x6: FloatOp::cvt_ps_s({{
1064 Fd_ud = (uint64_t) Fs_uw << 32 |
1071 0x5: CP1Unimpl::unknown();
1073 0x6: decode FUNCTION_LO {
1074 format FloatCompareOp {
1075 0x0: c_f_s({{ cond = 0; }},
1076 SinglePrecision, UnorderedFalse);
1077 0x1: c_un_s({{ cond = 0; }},
1078 SinglePrecision, UnorderedTrue);
1079 0x2: c_eq_s({{ cond = (Fs_sf == Ft_sf); }},
1081 0x3: c_ueq_s({{ cond = (Fs_sf == Ft_sf); }},
1083 0x4: c_olt_s({{ cond = (Fs_sf < Ft_sf); }},
1085 0x5: c_ult_s({{ cond = (Fs_sf < Ft_sf); }},
1087 0x6: c_ole_s({{ cond = (Fs_sf <= Ft_sf); }},
1089 0x7: c_ule_s({{ cond = (Fs_sf <= Ft_sf); }},
1094 0x7: decode FUNCTION_LO {
1095 format FloatCompareOp {
1096 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision,
1097 UnorderedFalse, QnanException);
1098 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision,
1099 UnorderedTrue, QnanException);
1100 0x2: c_seq_s({{ cond = (Fs_sf == Ft_sf); }},
1101 UnorderedFalse, QnanException);
1102 0x3: c_ngl_s({{ cond = (Fs_sf == Ft_sf); }},
1103 UnorderedTrue, QnanException);
1104 0x4: c_lt_s({{ cond = (Fs_sf < Ft_sf); }},
1105 UnorderedFalse, QnanException);
1106 0x5: c_nge_s({{ cond = (Fs_sf < Ft_sf); }},
1107 UnorderedTrue, QnanException);
1108 0x6: c_le_s({{ cond = (Fs_sf <= Ft_sf); }},
1109 UnorderedFalse, QnanException);
1110 0x7: c_ngt_s({{ cond = (Fs_sf <= Ft_sf); }},
1111 UnorderedTrue, QnanException);
1116 //Table A-15 MIPS32 COP1 Encoding of Function Field When
1118 0x1: decode FUNCTION_HI {
1119 0x0: decode FUNCTION_LO {
1121 0x0: add_d({{ Fd_df = Fs_df + Ft_df; }});
1122 0x1: sub_d({{ Fd_df = Fs_df - Ft_df; }});
1123 0x2: mul_d({{ Fd_df = Fs_df * Ft_df; }});
1124 0x3: div_d({{ Fd_df = Fs_df / Ft_df; }});
1125 0x4: sqrt_d({{ Fd_df = sqrt(Fs_df); }});
1126 0x5: abs_d({{ Fd_df = fabs(Fs_df); }});
1127 0x7: neg_d({{ Fd_df = -1 * Fs_df; }});
1129 0x6: BasicOp::mov_d({{ Fd_df = Fs_df; }});
1132 0x1: decode FUNCTION_LO {
1133 format FloatConvertOp {
1134 0x0: round_l_d({{ val = Fs_df; }},
1136 0x1: trunc_l_d({{ val = Fs_df; }},
1138 0x2: ceil_l_d({{ val = Fs_df; }},
1140 0x3: floor_l_d({{ val = Fs_df; }},
1142 0x4: round_w_d({{ val = Fs_df; }},
1144 0x5: trunc_w_d({{ val = Fs_df; }},
1146 0x6: ceil_w_d({{ val = Fs_df; }},
1148 0x7: floor_w_d({{ val = Fs_df; }},
1153 0x2: decode FUNCTION_LO {
1157 Fd_df = (getCondCode(FCSR,CC) == 0) ?
1161 Fd_df = (getCondCode(FCSR,CC) == 1) ?
1169 Fd_df = (Rt == 0) ? Fs_df : Fd_df;
1172 Fd_df = (Rt != 0) ? Fs_df : Fd_df;
1177 0x5: recip_d({{ Fd_df = 1 / Fs_df; }});
1178 0x6: rsqrt_d({{ Fd_df = 1 / sqrt(Fs_df); }});
1185 0x4: decode FUNCTION_LO {
1186 format FloatConvertOp {
1187 0x0: cvt_s_d({{ val = Fs_df; }}, ToSingle);
1188 0x4: cvt_w_d({{ val = Fs_df; }}, ToWord);
1189 0x5: cvt_l_d({{ val = Fs_df; }}, ToLong);
1191 default: CP1Unimpl::unknown();
1194 0x6: decode FUNCTION_LO {
1195 format FloatCompareOp {
1196 0x0: c_f_d({{ cond = 0; }},
1197 DoublePrecision, UnorderedFalse);
1198 0x1: c_un_d({{ cond = 0; }},
1199 DoublePrecision, UnorderedTrue);
1200 0x2: c_eq_d({{ cond = (Fs_df == Ft_df); }},
1202 0x3: c_ueq_d({{ cond = (Fs_df == Ft_df); }},
1204 0x4: c_olt_d({{ cond = (Fs_df < Ft_df); }},
1206 0x5: c_ult_d({{ cond = (Fs_df < Ft_df); }},
1208 0x6: c_ole_d({{ cond = (Fs_df <= Ft_df); }},
1210 0x7: c_ule_d({{ cond = (Fs_df <= Ft_df); }},
1215 0x7: decode FUNCTION_LO {
1216 format FloatCompareOp {
1217 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision,
1218 UnorderedFalse, QnanException);
1219 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision,
1220 UnorderedTrue, QnanException);
1221 0x2: c_seq_d({{ cond = (Fs_df == Ft_df); }},
1222 UnorderedFalse, QnanException);
1223 0x3: c_ngl_d({{ cond = (Fs_df == Ft_df); }},
1224 UnorderedTrue, QnanException);
1225 0x4: c_lt_d({{ cond = (Fs_df < Ft_df); }},
1226 UnorderedFalse, QnanException);
1227 0x5: c_nge_d({{ cond = (Fs_df < Ft_df); }},
1228 UnorderedTrue, QnanException);
1229 0x6: c_le_d({{ cond = (Fs_df <= Ft_df); }},
1230 UnorderedFalse, QnanException);
1231 0x7: c_ngt_d({{ cond = (Fs_df <= Ft_df); }},
1232 UnorderedTrue, QnanException);
1235 default: CP1Unimpl::unknown();
1237 0x2: CP1Unimpl::unknown();
1238 0x3: CP1Unimpl::unknown();
1239 0x7: CP1Unimpl::unknown();
1241 //Table A-16 MIPS32 COP1 Encoding of Function
1243 0x4: decode FUNCTION {
1244 format FloatConvertOp {
1245 0x20: cvt_s_w({{ val = Fs_uw; }}, ToSingle);
1246 0x21: cvt_d_w({{ val = Fs_uw; }}, ToDouble);
1247 0x26: CP1Unimpl::cvt_ps_w();
1249 default: CP1Unimpl::unknown();
1252 //Table A-16 MIPS32 COP1 Encoding of Function Field
1254 //Note: "1. Format type L is legal only if 64-bit
1255 //floating point operations are enabled."
1256 0x5: decode FUNCTION {
1257 format FloatConvertOp {
1258 0x20: cvt_s_l({{ val = Fs_ud; }}, ToSingle);
1259 0x21: cvt_d_l({{ val = Fs_ud; }}, ToDouble);
1260 0x26: CP1Unimpl::cvt_ps_l();
1262 default: CP1Unimpl::unknown();
1265 //Table A-17 MIPS64 COP1 Encoding of Function Field
1267 //Note: "1. Format type PS is legal only if 64-bit
1268 //floating point operations are enabled. "
1269 0x6: decode FUNCTION_HI {
1270 0x0: decode FUNCTION_LO {
1273 Fd1_sf = Fs1_sf + Ft2_sf;
1274 Fd2_sf = Fs2_sf + Ft2_sf;
1277 Fd1_sf = Fs1_sf - Ft2_sf;
1278 Fd2_sf = Fs2_sf - Ft2_sf;
1281 Fd1_sf = Fs1_sf * Ft2_sf;
1282 Fd2_sf = Fs2_sf * Ft2_sf;
1285 Fd1_sf = fabs(Fs1_sf);
1286 Fd2_sf = fabs(Fs2_sf);
1296 default: CP1Unimpl::unknown();
1299 0x1: CP1Unimpl::unknown();
1300 0x2: decode FUNCTION_LO {
1304 Fd1 = (getCondCode(FCSR, CC) == 0) ?
1306 Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
1310 Fd2 = (getCondCode(FCSR, CC) == 1) ?
1312 Fd2 = (getCondCode(FCSR, CC+1) == 1) ?
1320 Fd1 = (getCondCode(FCSR, CC) == 0) ?
1322 Fd2 = (getCondCode(FCSR, CC) == 0) ?
1326 Fd1 = (getCondCode(FCSR, CC) == 1) ?
1328 Fd2 = (getCondCode(FCSR, CC) == 1) ?
1332 default: CP1Unimpl::unknown();
1334 0x3: CP1Unimpl::unknown();
1335 0x4: decode FUNCTION_LO {
1336 0x0: FloatOp::cvt_s_pu({{ Fd_sf = Fs2_sf; }});
1337 default: CP1Unimpl::unknown();
1340 0x5: decode FUNCTION_LO {
1341 0x0: FloatOp::cvt_s_pl({{ Fd_sf = Fs1_sf; }});
1344 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft1_uw;
1347 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft2_uw;
1350 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft1_uw;
1353 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft2_uw;
1356 default: CP1Unimpl::unknown();
1359 0x6: decode FUNCTION_LO {
1360 format FloatPSCompareOp {
1361 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1363 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1365 0x2: c_eq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }},
1366 {{ cond2 = (Fs2_sf == Ft2_sf); }},
1368 0x3: c_ueq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }},
1369 {{ cond2 = (Fs2_sf == Ft2_sf); }},
1371 0x4: c_olt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }},
1372 {{ cond2 = (Fs2_sf < Ft2_sf); }},
1374 0x5: c_ult_ps({{ cond1 = (Fs_sf < Ft_sf); }},
1375 {{ cond2 = (Fs2_sf < Ft2_sf); }},
1377 0x6: c_ole_ps({{ cond1 = (Fs_sf <= Ft_sf); }},
1378 {{ cond2 = (Fs2_sf <= Ft2_sf); }},
1380 0x7: c_ule_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }},
1381 {{ cond2 = (Fs2_sf <= Ft2_sf); }},
1386 0x7: decode FUNCTION_LO {
1387 format FloatPSCompareOp {
1388 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1389 UnorderedFalse, QnanException);
1390 0x1: c_ngle_ps({{ cond1 = 0; }},
1392 UnorderedTrue, QnanException);
1393 0x2: c_seq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }},
1394 {{ cond2 = (Fs2_sf == Ft2_sf); }},
1395 UnorderedFalse, QnanException);
1396 0x3: c_ngl_ps({{ cond1 = (Fs1_sf == Ft1_sf); }},
1397 {{ cond2 = (Fs2_sf == Ft2_sf); }},
1398 UnorderedTrue, QnanException);
1399 0x4: c_lt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }},
1400 {{ cond2 = (Fs2_sf < Ft2_sf); }},
1401 UnorderedFalse, QnanException);
1402 0x5: c_nge_ps({{ cond1 = (Fs1_sf < Ft1_sf); }},
1403 {{ cond2 = (Fs2_sf < Ft2_sf); }},
1404 UnorderedTrue, QnanException);
1405 0x6: c_le_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }},
1406 {{ cond2 = (Fs2_sf <= Ft2_sf); }},
1407 UnorderedFalse, QnanException);
1408 0x7: c_ngt_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }},
1409 {{ cond2 = (Fs2_sf <= Ft2_sf); }},
1410 UnorderedTrue, QnanException);
1415 default: CP1Unimpl::unknown();
1419 //Table A-19 MIPS32 COP2 Encoding of rs Field
1420 0x2: decode RS_MSB {
1454 //Table A-20 MIPS64 COP1X Encoding of Function Field 1
1455 //Note: "COP1X instructions are legal only if 64-bit floating point
1456 //operations are enabled."
1457 0x3: decode FUNCTION_HI {
1458 0x0: decode FUNCTION_LO {
1459 format LoadIndexedMemory {
1460 0x0: lwxc1({{ Fd_uw = Mem_uw; }});
1461 0x1: ldxc1({{ Fd_ud = Mem_ud; }});
1462 0x5: luxc1({{ Fd_ud = Mem_ud; }},
1463 {{ EA = (Rs + Rt) & ~7; }});
1467 0x1: decode FUNCTION_LO {
1468 format StoreIndexedMemory {
1469 0x0: swxc1({{ Mem_uw = Fs_uw; }});
1470 0x1: sdxc1({{ Mem_ud = Fs_ud; }});
1471 0x5: suxc1({{ Mem_ud = Fs_ud; }},
1472 {{ EA = (Rs + Rt) & ~7; }});
1474 0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
1477 0x3: decode FUNCTION_LO {
1478 0x6: Float64Op::alnv_ps({{
1481 } else if (Rs<2:0> == 4) {
1482 if (GuestByteOrder == BigEndianByteOrder)
1483 Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>;
1485 Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>;
1493 0x4: decode FUNCTION_LO {
1494 0x0: madd_s({{ Fd_sf = (Fs_sf * Ft_sf) + Fr_sf; }});
1495 0x1: madd_d({{ Fd_df = (Fs_df * Ft_df) + Fr_df; }});
1497 Fd1_sf = (Fs1_df * Ft1_df) + Fr1_df;
1498 Fd2_sf = (Fs2_df * Ft2_df) + Fr2_df;
1502 0x5: decode FUNCTION_LO {
1503 0x0: msub_s({{ Fd_sf = (Fs_sf * Ft_sf) - Fr_sf; }});
1504 0x1: msub_d({{ Fd_df = (Fs_df * Ft_df) - Fr_df; }});
1506 Fd1_sf = (Fs1_df * Ft1_df) - Fr1_df;
1507 Fd2_sf = (Fs2_df * Ft2_df) - Fr2_df;
1511 0x6: decode FUNCTION_LO {
1512 0x0: nmadd_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) - Fr_sf; }});
1513 0x1: nmadd_d({{ Fd_df = (-1 * Fs_df * Ft_df) - Fr_df; }});
1515 Fd1_sf = -((Fs1_df * Ft1_df) + Fr1_df);
1516 Fd2_sf = -((Fs2_df * Ft2_df) + Fr2_df);
1520 0x7: decode FUNCTION_LO {
1521 0x0: nmsub_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) + Fr_sf; }});
1522 0x1: nmsub_d({{ Fd_df = (-1 * Fs_df * Ft_df) + Fr_df; }});
1524 Fd1_sf = -((Fs1_df * Ft1_df) - Fr1_df);
1525 Fd2_sf = -((Fs2_df * Ft2_df) - Fr2_df);
1532 0x4: beql({{ cond = (Rs_sw == Rt_sw); }}, Likely);
1533 0x5: bnel({{ cond = (Rs_sw != Rt_sw); }}, Likely);
1534 0x6: blezl({{ cond = (Rs_sw <= 0); }}, Likely);
1535 0x7: bgtzl({{ cond = (Rs_sw > 0); }}, Likely);
1539 0x3: decode OPCODE_LO {
1540 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1541 0x4: decode FUNCTION_HI {
1542 0x0: decode FUNCTION_LO {
1544 int64_t temp1 = Rs_sd * Rt_sd;
1545 Rd_sw = temp1<31:0>;
1548 format HiLoRdSelValOp {
1550 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) +
1554 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) +
1558 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) -
1562 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) -
1568 0x4: decode FUNCTION_LO {
1572 for (int idx = 31; idx >= 0; idx--) {
1573 if (Rs<idx:idx> == 1) {
1582 for (int idx = 31; idx >= 0; idx--) {
1583 if (Rs<idx:idx> == 0) {
1593 0x7: decode FUNCTION_LO {
1594 0x7: FailUnimpl::sdbbp();
1598 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2
1599 //of the Architecture
1600 0x7: decode FUNCTION_HI {
1601 0x0: decode FUNCTION_LO {
1603 0x0: ext({{ Rt_uw = bits(Rs_uw, MSB+LSB, LSB); }});
1605 Rt_uw = bits(Rt_uw, 31, MSB+1) << (MSB+1) |
1606 bits(Rs_uw, MSB-LSB, 0) << LSB |
1607 bits(Rt_uw, LSB-1, 0);
1612 0x1: decode FUNCTION_LO {
1615 forkThread(xc->tcBase(), fault, RD, Rs, Rt);
1618 Rd_sw = yieldThread(xc->tcBase(), fault, Rs_sw,
1623 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL)
1626 format LoadIndexedMemory {
1627 0x0: lwx({{ Rd_sw = Mem_sw; }});
1628 0x4: lhx({{ Rd_sw = Mem_sh; }});
1629 0x6: lbux({{ Rd_uw = Mem_ub; }});
1633 0x4: DspIntOp::insv({{
1634 int pos = dspctl<5:0>;
1635 int size = dspctl<12:7> - 1;
1636 Rt_uw = insertBits(Rt_uw, pos+size,
1637 pos, Rs_uw<size:0>);
1641 0x2: decode FUNCTION_LO {
1643 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field
1649 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB,
1650 NOSATURATE, UNSIGNED, &dspctl);
1653 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB,
1654 NOSATURATE, UNSIGNED, &dspctl);
1657 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB,
1658 SATURATE, UNSIGNED, &dspctl);
1661 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB,
1662 SATURATE, UNSIGNED, &dspctl);
1664 0x6: muleu_s_ph_qbl({{
1665 Rd_uw = dspMuleu(Rs_uw, Rt_uw,
1668 0x7: muleu_s_ph_qbr({{
1669 Rd_uw = dspMuleu(Rs_uw, Rt_uw,
1677 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH,
1678 NOSATURATE, UNSIGNED, &dspctl);
1681 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH,
1682 NOSATURATE, UNSIGNED, &dspctl);
1685 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH,
1686 NOSATURATE, SIGNED, &dspctl);
1689 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH,
1690 NOSATURATE, SIGNED, &dspctl);
1693 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH,
1694 SATURATE, UNSIGNED, &dspctl);
1697 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH,
1698 SATURATE, UNSIGNED, &dspctl);
1701 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH,
1702 SATURATE, SIGNED, &dspctl);
1705 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH,
1706 SATURATE, SIGNED, &dspctl);
1714 dresult = Rs_ud + Rt_ud;
1715 Rd_sw = dresult<31:0>;
1716 dspctl = insertBits(dspctl, 13, 13,
1721 dresult = Rs_sd + Rt_sd + dspctl<13:13>;
1722 Rd_sw = dresult<31:0>;
1723 if (dresult<32:32> != dresult<31:31>)
1724 dspctl = insertBits(dspctl, 20, 20, 1);
1727 Rd_sw = (Rs_sw == 0) ? Rt_sw<23:8> :
1731 Rd_uw = Rs_uw<31:24> + Rs_uw<23:16> +
1732 Rs_uw<15:8> + Rs_uw<7:0>;
1735 Rd_sw = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W,
1736 SATURATE, SIGNED, &dspctl);
1739 Rd_sw = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W,
1740 SATURATE, SIGNED, &dspctl);
1746 0x4: muleq_s_w_phl({{
1747 Rd_sw = dspMuleq(Rs_sw, Rt_sw,
1750 0x5: muleq_s_w_phr({{
1751 Rd_sw = dspMuleq(Rs_sw, Rt_sw,
1755 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH,
1756 SATURATE, NOROUND, &dspctl);
1759 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH,
1760 SATURATE, ROUND, &dspctl);
1766 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field
1772 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB,
1773 UNSIGNED, CMP_EQ, &dspctl);
1776 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB,
1777 UNSIGNED, CMP_LT, &dspctl);
1780 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB,
1781 UNSIGNED, CMP_LE, &dspctl);
1784 Rd_uw = dspPick(Rs_uw, Rt_uw,
1785 SIMD_FMT_QB, &dspctl);
1788 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB,
1792 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB,
1796 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB,
1804 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH,
1805 SIGNED, CMP_EQ, &dspctl);
1808 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH,
1809 SIGNED, CMP_LT, &dspctl);
1812 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH,
1813 SIGNED, CMP_LE, &dspctl);
1816 Rd_uw = dspPick(Rs_uw, Rt_uw,
1817 SIMD_FMT_PH, &dspctl);
1819 0x4: precrq_qb_ph({{
1820 Rd_uw = Rs_uw<31:24> << 24 |
1826 Rd_uw = Rs_uw<23:16> << 24 |
1832 Rd_uw = dspPack(Rs_uw, Rt_uw, SIMD_FMT_PH);
1834 0x7: precrqu_s_qb_ph({{
1835 Rd_uw = dspPrecrqu(Rs_uw, Rt_uw, &dspctl);
1842 Rd_uw = Rs_uw<31:16> << 16 | Rt_uw<31:16>;
1844 0x5: precrq_rs_ph_w({{
1845 Rd_uw = dspPrecrq(Rs_uw, Rt_uw,
1846 SIMD_FMT_W, &dspctl);
1852 0x0: cmpgdu_eq_qb({{
1853 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB,
1854 UNSIGNED, CMP_EQ, &dspctl);
1856 0x1: cmpgdu_lt_qb({{
1857 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB,
1858 UNSIGNED, CMP_LT, &dspctl);
1860 0x2: cmpgdu_le_qb({{
1861 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB,
1862 UNSIGNED, CMP_LE, &dspctl);
1864 0x6: precr_sra_ph_w({{
1865 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD,
1866 SIMD_FMT_W, NOROUND);
1868 0x7: precr_sra_r_ph_w({{
1869 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD,
1876 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field
1882 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl);
1885 Rd_uw = RS_RT<7:0> << 24 |
1891 Rd_sw = Rt_uw<7:0> << 24 |
1896 0x4: precequ_ph_qbl({{
1897 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED,
1898 SIMD_FMT_PH, SIGNED, MODE_L);
1900 0x5: precequ_ph_qbr({{
1901 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED,
1902 SIMD_FMT_PH, SIGNED, MODE_R);
1904 0x6: precequ_ph_qbla({{
1905 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED,
1906 SIMD_FMT_PH, SIGNED, MODE_LA);
1908 0x7: precequ_ph_qbra({{
1909 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED,
1910 SIMD_FMT_PH, SIGNED, MODE_RA);
1917 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl);
1920 Rd_uw = (sext<10>(RS_RT))<15:0> << 16 |
1921 (sext<10>(RS_RT))<15:0>;
1924 Rd_uw = Rt_uw<15:0> << 16 |
1927 0x4: preceq_w_phl({{
1928 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED,
1929 SIMD_FMT_W, SIGNED, MODE_L);
1931 0x5: preceq_w_phr({{
1932 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED,
1933 SIMD_FMT_W, SIGNED, MODE_R);
1940 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl);
1945 0x3: IntOp::bitrev({{
1946 Rd_uw = bitrev( Rt_uw<15:0> );
1949 0x4: preceu_ph_qbl({{
1950 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB,
1951 UNSIGNED, SIMD_FMT_PH,
1954 0x5: preceu_ph_qbr({{
1955 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB,
1956 UNSIGNED, SIMD_FMT_PH,
1959 0x6: preceu_ph_qbla({{
1960 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB,
1961 UNSIGNED, SIMD_FMT_PH,
1962 UNSIGNED, MODE_LA );
1964 0x7: preceu_ph_qbra({{
1965 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB,
1966 UNSIGNED, SIMD_FMT_PH,
1973 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field
1979 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_QB,
1980 NOSATURATE, UNSIGNED, &dspctl);
1983 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_QB,
1987 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB,
1988 NOSATURATE, UNSIGNED, &dspctl);
1991 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB,
1995 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB,
1996 NOROUND, SIGNED, &dspctl);
1999 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB,
2000 ROUND, SIGNED, &dspctl);
2003 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB,
2004 NOROUND, SIGNED, &dspctl);
2007 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB,
2008 ROUND, SIGNED, &dspctl);
2015 Rd_uw = dspShll(Rt_uw, RS, SIMD_FMT_PH,
2016 NOSATURATE, SIGNED, &dspctl);
2019 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH,
2020 NOROUND, SIGNED, &dspctl);
2023 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH,
2024 NOSATURATE, SIGNED, &dspctl);
2027 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH,
2028 NOROUND, SIGNED, &dspctl);
2031 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_PH,
2032 SATURATE, SIGNED, &dspctl);
2035 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH,
2036 ROUND, SIGNED, &dspctl);
2039 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH,
2040 SATURATE, SIGNED, &dspctl);
2043 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH,
2044 ROUND, SIGNED, &dspctl);
2051 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_W,
2052 SATURATE, SIGNED, &dspctl);
2055 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_W,
2056 ROUND, SIGNED, &dspctl);
2059 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W,
2060 SATURATE, SIGNED, &dspctl);
2063 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W,
2064 ROUND, SIGNED, &dspctl);
2071 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_PH,
2075 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH,
2083 0x3: decode FUNCTION_LO {
2085 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field
2086 //(DSP ASE Rev2 Manual)
2091 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2095 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2099 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2103 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB,
2111 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2115 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2119 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2123 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH,
2127 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH,
2128 NOSATURATE, &dspctl);
2131 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH,
2139 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W,
2143 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W,
2147 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W,
2151 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W,
2155 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W,
2156 SATURATE, NOROUND, &dspctl);
2159 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W,
2160 SATURATE, ROUND, &dspctl);
2167 //Table A-10 MIPS32 BSHFL Encoding of sa Field
2171 Rd_uw = Rt_uw<23:16> << 24 |
2172 Rt_uw<31:24> << 16 |
2176 0x10: seb({{ Rd_sw = Rt_sb; }});
2177 0x18: seh({{ Rd_sw = Rt_sh; }});
2181 0x6: decode FUNCTION_LO {
2183 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field
2189 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST,
2190 SIMD_FMT_PH, SIGNED, MODE_L);
2193 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST,
2194 SIMD_FMT_PH, SIGNED, MODE_L);
2197 dspac = dspMulsa(dspac, Rs_sw, Rt_sw,
2198 ACDST, SIMD_FMT_PH );
2201 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST,
2202 SIMD_FMT_QB, UNSIGNED, MODE_L);
2205 dspac = dspDpaq(dspac, Rs_sw, Rt_sw,
2207 SIMD_FMT_W, NOSATURATE,
2211 dspac = dspDpsq(dspac, Rs_sw, Rt_sw,
2213 SIMD_FMT_W, NOSATURATE,
2216 0x6: mulsaq_s_w_ph({{
2217 dspac = dspMulsaq(dspac, Rs_sw, Rt_sw,
2222 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST,
2223 SIMD_FMT_QB, UNSIGNED, MODE_R);
2230 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST,
2231 SIMD_FMT_PH, SIGNED, MODE_X);
2234 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST,
2235 SIMD_FMT_PH, SIGNED, MODE_X);
2238 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST,
2239 SIMD_FMT_QB, UNSIGNED, MODE_L);
2242 dspac = dspDpaq(dspac, Rs_sw, Rt_sw,
2244 SIMD_FMT_L, SATURATE,
2248 dspac = dspDpsq(dspac, Rs_sw, Rt_sw,
2250 SIMD_FMT_L, SATURATE,
2254 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST,
2255 SIMD_FMT_QB, UNSIGNED, MODE_R);
2261 0x0: maq_sa_w_phl({{
2262 dspac = dspMaq(dspac, Rs_uw, Rt_uw,
2264 MODE_L, SATURATE, &dspctl);
2266 0x2: maq_sa_w_phr({{
2267 dspac = dspMaq(dspac, Rs_uw, Rt_uw,
2269 MODE_R, SATURATE, &dspctl);
2272 dspac = dspMaq(dspac, Rs_uw, Rt_uw,
2274 MODE_L, NOSATURATE, &dspctl);
2277 dspac = dspMaq(dspac, Rs_uw, Rt_uw,
2279 MODE_R, NOSATURATE, &dspctl);
2285 0x0: dpaqx_s_w_ph({{
2286 dspac = dspDpaq(dspac, Rs_sw, Rt_sw,
2288 SIMD_FMT_W, NOSATURATE,
2291 0x1: dpsqx_s_w_ph({{
2292 dspac = dspDpsq(dspac, Rs_sw, Rt_sw,
2294 SIMD_FMT_W, NOSATURATE,
2297 0x2: dpaqx_sa_w_ph({{
2298 dspac = dspDpaq(dspac, Rs_sw, Rt_sw,
2300 SIMD_FMT_W, SATURATE,
2303 0x3: dpsqx_sa_w_ph({{
2304 dspac = dspDpsq(dspac, Rs_sw, Rt_sw,
2306 SIMD_FMT_W, SATURATE,
2313 //Table 3.3 MIPS32 APPEND Encoding of the op Field
2318 Rt_uw = (Rt_uw << RD) | bits(Rs_uw, RD - 1, 0);
2321 Rt_uw = (Rt_uw >> RD) |
2322 (bits(Rs_uw, RD - 1, 0) << (32 - RD));
2329 Rt_uw = (Rt_uw << (8 * BP)) |
2330 (Rs_uw >> (8 * (4 - BP)));
2337 0x7: decode FUNCTION_LO {
2339 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field
2345 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS,
2346 NOROUND, NOSATURATE, &dspctl);
2349 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw,
2350 NOROUND, NOSATURATE, &dspctl);
2353 Rt_uw = dspExtp(dspac, RS, &dspctl);
2356 Rt_uw = dspExtp(dspac, Rs_uw, &dspctl);
2359 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS,
2360 ROUND, NOSATURATE, &dspctl);
2363 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw,
2364 ROUND, NOSATURATE, &dspctl);
2367 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS,
2368 ROUND, SATURATE, &dspctl);
2371 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw,
2372 ROUND, SATURATE, &dspctl);
2379 Rt_uw = dspExtpd(dspac, RS, &dspctl);
2382 Rt_uw = dspExtpd(dspac, Rs_uw, &dspctl);
2385 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, RS,
2386 NOROUND, SATURATE, &dspctl);
2389 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, Rs_uw,
2390 NOROUND, SATURATE, &dspctl);
2397 Rd_uw = readDSPControl(&dspctl, RDDSPMASK);
2400 writeDSPControl(&dspctl, Rs_uw, WRDSPMASK);
2407 if (sext<6>(HILOSA) < 0) {
2408 dspac = (uint64_t)dspac <<
2411 dspac = (uint64_t)dspac >>
2416 if (sext<6>(Rs_sw<5:0>) < 0) {
2417 dspac = (uint64_t)dspac <<
2418 -sext<6>(Rs_sw<5:0>);
2420 dspac = (uint64_t)dspac >>
2421 sext<6>(Rs_sw<5:0>);
2425 dspac = dspac << 32;
2427 dspctl = insertBits(dspctl, 5, 0,
2433 0x3: decode OP default FailUnimpl::rdhwr() {
2434 0x0: decode FULL_SYSTEM {
2436 29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
2444 0x4: decode OPCODE_LO {
2446 0x0: lb({{ Rt_sw = Mem_sb; }});
2447 0x1: lh({{ Rt_sw = Mem_sh; }});
2448 0x3: lw({{ Rt_sw = Mem_sw; }});
2449 0x4: lbu({{ Rt_uw = Mem_ub;}});
2450 0x5: lhu({{ Rt_uw = Mem_uh; }});
2453 format LoadUnalignedMemory {
2455 uint32_t mem_shift = 24 - (8 * byte_offset);
2456 Rt_uw = mem_word << mem_shift | (Rt_uw & mask(mem_shift));
2459 uint32_t mem_shift = 8 * byte_offset;
2460 Rt_uw = (Rt_uw & (mask(mem_shift) << (32 - mem_shift))) |
2461 (mem_word >> mem_shift);
2466 0x5: decode OPCODE_LO {
2467 format StoreMemory {
2468 0x0: sb({{ Mem_ub = Rt<7:0>; }});
2469 0x1: sh({{ Mem_uh = Rt<15:0>; }});
2470 0x3: sw({{ Mem_uw = Rt<31:0>; }});
2473 format StoreUnalignedMemory {
2475 uint32_t reg_shift = 24 - (8 * byte_offset);
2476 uint32_t mem_shift = 32 - reg_shift;
2477 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) |
2478 (Rt_uw >> reg_shift);
2481 uint32_t reg_shift = 8 * byte_offset;
2482 mem_word = Rt_uw << reg_shift |
2483 (mem_word & (mask(reg_shift)));
2488 //Addr CacheEA = Rs_uw + OFFSET;
2489 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA);
2494 0x6: decode OPCODE_LO {
2496 0x0: ll({{ Rt_uw = Mem_uw; }}, mem_flags=LLSC);
2497 0x1: lwc1({{ Ft_uw = Mem_uw; }});
2498 0x5: ldc1({{ Ft_ud = Mem_ud; }});
2500 0x2: CP2Unimpl::lwc2();
2501 0x6: CP2Unimpl::ldc2();
2502 0x3: Prefetch::pref();
2506 0x7: decode OPCODE_LO {
2507 0x0: StoreCond::sc({{ Mem_uw = Rt_uw; }},
2508 {{ uint64_t tmp = write_result;
2509 Rt_uw = (tmp == 0 || tmp == 1) ? tmp : Rt_uw;
2511 inst_flags = IsStoreConditional);
2512 format StoreMemory {
2513 0x1: swc1({{ Mem_uw = Ft_uw; }});
2514 0x5: sdc1({{ Mem_ud = Ft_ud; }});
2516 0x2: CP2Unimpl::swc2();
2517 0x6: CP2Unimpl::sdc2();