3 // Copyright (c) 2007 MIPS Technologies, Inc.
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Korey Sewell
32 ////////////////////////////////////////////////////////////////////
34 // Coprocessor instructions
37 //Outputs to decoder.hh
40 class CP0Control : public MipsStaticInst
45 CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
46 MipsStaticInst(mnem, _machInst, __opClass)
50 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
52 class CP0TLB : public MipsStaticInst
57 CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) :
58 MipsStaticInst(mnem, _machInst, __opClass)
62 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
66 class CP1Control : public MipsStaticInst
71 CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
72 MipsStaticInst(mnem, _machInst, __opClass)
76 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
81 // Basic instruction class execute method template.
82 def template CP0Execute {{
83 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
85 Fault fault = NoFault;
89 if (isCoprocessorEnabled(xc, 0)) {
97 fault = new CoprocessorUnusableFault(0);
103 def template CP1Execute {{
104 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
106 Fault fault = NoFault;
110 if (isCoprocessorEnabled(xc, 1)) {
113 fault = new CoprocessorUnusableFault(1);
123 // Basic instruction class execute method template.
124 def template ControlTLBExecute {{
125 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
127 Fault fault = NoFault;
132 if (isCoprocessor0Enabled(xc)) {
136 fault = new ReservedInstructionFault();
139 fault = new CoprocessorUnusableFault(0);
141 } else { // Syscall Emulation Mode - No TLB Instructions
142 fault = new ReservedInstructionFault();
145 if (fault == NoFault) {
152 //Outputs to decoder.cc
154 std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
156 std::stringstream ss;
157 ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
160 std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const
162 std::stringstream ss;
163 ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
166 std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
168 std::stringstream ss;
169 ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
176 bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num);
178 bool isMMUTLB(%(CPU_exec_context)s *xc);
184 isCoprocessorEnabled(CPU_EXEC_CONTEXT *xc, unsigned cop_num)
189 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
191 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
192 // In Stat, EXL, ERL or CU0 set, CP0 accessible
193 // In Dbg, DM bit set, CP0 accessible
194 // In Stat, KSU = 0, kernel mode is base mode
195 return (Stat & 0x10000006) ||
196 (Dbg & 0x40000000) ||
197 !(Stat & 0x00000018);
198 } else if (cop_num < 4) {
199 return Stat & (0x10000000 << cop_num); // CU is reset
201 panic("Invalid Coprocessor Number Specified");
206 isCoprocessor0Enabled(CPU_EXEC_CONTEXT *xc)
209 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
210 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
211 // In Stat, EXL, ERL or CU0 set, CP0 accessible
212 // In Dbg, DM bit set, CP0 accessible
213 // In Stat KSU = 0, kernel mode is base mode
214 return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
215 !(Stat & 0x00000018);
222 isMMUTLB(CPU_EXEC_CONTEXT *xc)
224 MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
225 return FullSystem && (Config & 0x380) == 0x80;
229 def format CP0Control(code, *flags) {{
230 flags += ('IsNonSpeculative', )
231 iop = InstObjParams(name, Name, 'CP0Control', code, flags)
232 header_output = BasicDeclare.subst(iop)
233 decoder_output = BasicConstructor.subst(iop)
234 decode_block = BasicDecode.subst(iop)
235 exec_output = CP0Execute.subst(iop)
237 def format CP0TLB(code, *flags) {{
238 flags += ('IsNonSpeculative', )
239 iop = InstObjParams(name, Name, 'CP0Control', code, flags)
240 header_output = BasicDeclare.subst(iop)
241 decoder_output = BasicConstructor.subst(iop)
242 decode_block = BasicDecode.subst(iop)
243 exec_output = ControlTLBExecute.subst(iop)
245 def format CP1Control(code, *flags) {{
246 flags += ('IsNonSpeculative', )
247 iop = InstObjParams(name, Name, 'CP1Control', code, flags)
248 header_output = BasicDeclare.subst(iop)
249 decoder_output = BasicConstructor.subst(iop)
250 decode_block = BasicDecode.subst(iop)
251 exec_output = CP1Execute.subst(iop)