84deeb9dbeece7fb57c9e266172050a3ba55b4a0
[gem5.git] / src / arch / mips / isa / formats / dsp.isa
1 // -*- mode:c++ -*-
2
3 // Copyright \eN) 2007 MIPS Technologies, Inc. All Rights Reserved
4
5 // This software is part of the M5 simulator.
6
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8 // DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
9 // TO THESE TERMS AND CONDITIONS.
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18 // the name of MIPS Technologies, Inc. (\e$(B!H\e(BMIPS\e$(B!I\e(B) is not used in any
19 // advertising or publicity pertaining to the use or distribution of
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22 // THIS SOFTWARE IS PROVIDED \e$(B!H\e(BAS IS.\e$(B!I\e(B MIPS MAKES NO WARRANTIES AND
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30 // THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
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34
35 //Authors: Korey L. Sewell
36 // Brett Miller
37
38 ////////////////////////////////////////////////////////////////////
39 //
40 // DSP integer operate instructions
41 //
42 output header {{
43 #include <iostream>
44 using namespace std;
45 /**
46 * Base class for integer operations.
47 */
48 class DspIntOp : public MipsStaticInst
49 {
50 protected:
51
52 /// Constructor
53 DspIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
54 MipsStaticInst(mnem, _machInst, __opClass)
55 {
56 }
57 };
58
59 class DspHiLoOp : public MipsStaticInst
60 {
61 protected:
62
63 /// Constructor
64 DspHiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
65 MipsStaticInst(mnem, _machInst, __opClass)
66 {
67 }
68 };
69 }};
70
71 // Dsp instruction class execute method template.
72 def template DspExecute {{
73 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
74 {
75 Fault fault = NoFault;
76
77 %(op_decl)s;
78
79 if (isDspPresent(xc))
80 {
81 if (isDspEnabled(xc))
82 {
83 %(op_rd)s;
84 %(code)s;
85 }
86 else
87 {
88 fault = new DspStateDisabledFault();
89 }
90 }
91 else
92 {
93 fault = new ReservedInstructionFault();
94 }
95
96 if(fault == NoFault)
97 {
98 %(op_wb)s;
99 }
100 return fault;
101 }
102 }};
103
104 // DspHiLo instruction class execute method template.
105 def template DspHiLoExecute {{
106 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
107 {
108 Fault fault = NoFault;
109
110 %(op_decl)s;
111
112 if (isDspPresent(xc))
113 {
114 if (isDspEnabled(xc))
115 {
116 %(op_rd)s;
117 %(code)s;
118 }
119 else
120 {
121 fault = new DspStateDisabledFault();
122 }
123 }
124 else
125 {
126 fault = new ReservedInstructionFault();
127 }
128
129 if(fault == NoFault)
130 {
131 %(op_wb)s;
132 //If there are 2 Destination Registers then
133 //concatenate the values for the traceData
134 if(traceData && _numDestRegs == 2) {
135 // FIXME - set the trace value correctly here
136 //uint64_t hilo_final_val = (uint64_t)HI_RD_SEL << 32 | LO_RD_SEL;
137 //traceData->setData(hilo_final_val);
138 }
139 }
140 return fault;
141 }
142 }};
143
144 //Outputs to decoder.cc
145 output decoder {{
146 }};
147
148 output exec {{
149 bool isDspEnabled(%(CPU_exec_context)s *xc)
150 {
151 #if FULL_SYSTEM
152 if( bits( xc->readMiscReg(MipsISA::Status), 24, 24 ) == 0 )
153 return false;
154 #else
155 //printf("Syscall Emulation Mode: isDspEnabled() check defaults to TRUE\n");
156 #endif
157 return true;
158 }
159 }};
160
161 output exec {{
162 bool isDspPresent(%(CPU_exec_context)s *xc)
163 {
164 #if FULL_SYSTEM
165 if( bits( xc->readMiscReg(MipsISA::Config3), 10, 10 ) == 0 )
166 return false;
167 #else
168 //printf("Syscall Emulation Mode: isDspPresent() check defaults to TRUE\n");
169 #endif
170 return true;
171 }
172 }};
173
174 // add code to fetch the DSPControl register
175 // and write it back after execution, giving
176 // the instruction the opportunity to modify
177 // it if necessary
178 def format DspIntOp(code, *opt_flags) {{
179
180 decl_code = 'uint32_t dspctl;\n'
181 decl_code += 'dspctl = DSPControl;\n'
182
183 write_code = 'DSPControl = dspctl;\n'
184
185 code = decl_code + code + write_code
186
187 opt_flags += ('IsDspOp',)
188
189 iop = InstObjParams(name, Name, 'DspIntOp', code, opt_flags)
190 header_output = BasicDeclare.subst(iop)
191 decoder_output = BasicConstructor.subst(iop)
192 decode_block = BasicDecode.subst(iop)
193 exec_output = DspExecute.subst(iop)
194 }};
195
196 // add code to fetch the DSPControl register
197 // and write it back after execution, giving
198 // the instruction the opportunity to modify
199 // it if necessary; also, fetch the appropriate
200 // HI/LO register pair, based on the AC
201 // instruction field.
202
203 def format DspHiLoOp(code, *opt_flags) {{
204
205 decl_code = 'int64_t dspac;\n'
206 decl_code += 'uint32_t dspctl;\n'
207
208 fetch_code = 'dspctl = DSPControl;\n'
209 fetch_code += 'dspac = HI_RD_SEL;\n'
210 fetch_code += 'dspac = dspac << 32 | LO_RD_SEL;\n'
211
212 write_code = 'DSPControl = dspctl;\n'
213 write_code += 'HI_RD_SEL = dspac<63:32>;\n'
214 write_code += 'LO_RD_SEL = dspac<31:0>;\n'
215
216 code = decl_code + fetch_code + code + write_code
217
218 opt_flags += ('IsDspOp',)
219
220 iop = InstObjParams(name, Name, 'DspHiLoOp', code, opt_flags)
221 header_output = BasicDeclare.subst(iop)
222 decoder_output = BasicConstructor.subst(iop)
223 decode_block = BasicDecode.subst(iop)
224 exec_output = DspHiLoExecute.subst(iop)
225
226 }};
227
228
229