src/arch/mips/isa/formats/fp.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2007 MIPS Technologies, Inc.
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 ////////////////////////////////////////////////////////////////////
  30 //
  31 // Floating Point operate instructions
  32 //
  33
  34 output header {{
  35     /**
  36      * Base class for FP operations.
  37      */
  38     class FPOp : public MipsStaticInst
  39     {
  40       protected:
  41         using MipsStaticInst::MipsStaticInst;
  42
  43         //needs function to check for fpEnable or not
  44     };
  45
  46     class FPCompareOp : public FPOp
  47     {
  48       protected:
  49         using FPOp::FPOp;
  50
  51         std::string generateDisassembly(
  52                 Addr pc, const Loader::SymbolTable *symtab) const override;
  53     };
  54 }};
  55
  56 output decoder {{
  57     std::string
  58     FPCompareOp::generateDisassembly(
  59             Addr pc, const Loader::SymbolTable *symtab) const
  60     {
  61         std::stringstream ss;
  62
  63         ccprintf(ss, "%-10s ", mnemonic);
  64
  65         ccprintf(ss,"%d",CC);
  66
  67         if (_numSrcRegs > 0) {
  68             ss << ", ";
  69             printReg(ss, srcRegIdx(0));
  70         }
  71
  72         if (_numSrcRegs > 1) {
  73             ss << ", ";
  74             printReg(ss, srcRegIdx(1));
  75         }
  76
  77         return ss.str();
  78     }
  79 }};
  80
  81 output header {{
  82     void fpResetCauseBits(ExecContext *cpu);
  83 }};
  84
  85 output exec {{
  86     inline Fault
  87     checkFpEnableFault(ExecContext *xc)
  88     {
  89         //@TODO: Implement correct CP0 checks to see if the CP1
  90         // unit is enable or not
  91         if (!isCoprocessorEnabled(xc, 1))
  92             return std::make_shared<CoprocessorUnusableFault>(1);
  93
  94         return NoFault;
  95     }
  96
  97     //If any operand is Nan return the appropriate QNaN
  98     template <class T>
  99     bool
 100     fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type,
 101                   Trace::InstRecord *traceData)
 102     {
 103         uint64_t mips_nan = 0;
 104         assert(sizeof(T) == 4);
 105
 106         for (int i = 0; i < inst->numSrcRegs(); i++) {
 107             uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0);
 108
 109             if (isNan(&src_bits, 32) ) {
 110                 mips_nan = MIPS32_QNAN;
 111                 xc->setFloatRegOperandBits(inst, 0, mips_nan);
 112                 if (traceData) { traceData->setData(mips_nan); }
 113                 return true;
 114             }
 115         }
 116         return false;
 117     }
 118
 119     template <class T>
 120     bool
 121     fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val,
 122                 Trace::InstRecord *traceData)
 123     {
 124         uint64_t mips_nan = 0;
 125         T src_op = dest_val;
 126         assert(sizeof(T) == 4);
 127
 128         if (isNan(&src_op, 32)) {
 129             mips_nan = MIPS32_QNAN;
 130
 131             //Set value to QNAN
 132             cpu->setFloatRegOperandBits(inst, 0, mips_nan);
 133
 134             //Read FCSR from FloatRegFile
 135             uint32_t fcsr_bits =
 136                 cpu->tcBase()->readFloatReg(FLOATREG_FCSR);
 137
 138             uint32_t new_fcsr = genInvalidVector(fcsr_bits);
 139
 140             //Write FCSR from FloatRegFile
 141             cpu->tcBase()->setFloatReg(FLOATREG_FCSR, new_fcsr);
 142
 143             if (traceData) { traceData->setData(mips_nan); }
 144             return true;
 145         }
 146
 147         return false;
 148     }
 149
 150     void
 151     fpResetCauseBits(ExecContext *cpu)
 152     {
 153         //Read FCSR from FloatRegFile
 154         uint32_t fcsr = cpu->tcBase()->readFloatReg(FLOATREG_FCSR);
 155
 156         // TODO: Use utility function here
 157         fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
 158
 159         //Write FCSR from FloatRegFile
 160         cpu->tcBase()->setFloatReg(FLOATREG_FCSR, fcsr);
 161     }
 162 }};
 163
 164 def template FloatingPointExecute {{
 165     Fault %(class_name)s::execute(
 166         ExecContext *xc, Trace::InstRecord *traceData) const
 167     {
 168         Fault fault = NoFault;
 169
 170         %(fp_enable_check)s;
 171
 172         //When is the right time to reset cause bits?
 173         //start of every instruction or every cycle?
 174         if (FullSystem)
 175             fpResetCauseBits(xc);
 176         %(op_decl)s;
 177         %(op_rd)s;
 178
 179         //Check if any FP operand is a NaN value
 180         if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
 181             %(code)s;
 182
 183             //Change this code for Full-System/Sycall Emulation
 184             //separation
 185             //----
 186             //Should Full System-Mode throw a fault here?
 187             //----
 188             //Check for IEEE 754 FP Exceptions
 189             //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
 190             bool invalid_op = false;
 191             if (FullSystem) {
 192                 invalid_op =
 193                     fpInvalidOp((FPOp*)this, xc, Fd, traceData);
 194             }
 195             if (!invalid_op && fault == NoFault) {
 196                 %(op_wb)s;
 197             }
 198         }
 199
 200         return fault;
 201     }
 202 }};
 203
 204 // Primary format for float point operate instructions:
 205 def format FloatOp(code, *flags) {{
 206     iop = InstObjParams(name, Name, 'FPOp', code, flags)
 207     header_output = BasicDeclare.subst(iop)
 208     decoder_output = BasicConstructor.subst(iop)
 209     decode_block = BasicDecode.subst(iop)
 210     exec_output = FloatingPointExecute.subst(iop)
 211 }};
 212
 213 def format FloatCompareOp(cond_code, *flags) {{
 214     import sys
 215
 216     code = 'bool cond;\n'
 217     if '_sf' in cond_code or 'SinglePrecision' in flags:
 218         if 'QnanException' in flags:
 219             code += 'if (isQnan(&Fs_sf, 32) || isQnan(&Ft_sf, 32)) {\n'
 220             code += '\tFCSR = genInvalidVector(FCSR);\n'
 221             code += '\treturn NoFault;'
 222             code += '}\n else '
 223         code += 'if (isNan(&Fs_sf, 32) || isNan(&Ft_sf, 32)) {\n'
 224     elif '_df' in cond_code or 'DoublePrecision' in flags:
 225         if 'QnanException' in flags:
 226             code += 'if (isQnan(&Fs_df, 64) || isQnan(&Ft_df, 64)) {\n'
 227             code += '\tFCSR = genInvalidVector(FCSR);\n'
 228             code += '\treturn NoFault;'
 229             code += '}\n else '
 230         code += 'if (isNan(&Fs_df, 64) || isNan(&Ft_df, 64)) {\n'
 231     else:
 232        sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
 233
 234     if 'UnorderedTrue' in flags:
 235        code += 'cond = 1;\n'
 236     elif 'UnorderedFalse' in flags:
 237        code += 'cond = 0;\n'
 238     else:
 239        sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
 240
 241     code += '} else {\n'
 242     code +=  cond_code + '}'
 243     code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
 244
 245     iop = InstObjParams(name, Name, 'FPCompareOp', code)
 246     header_output = BasicDeclare.subst(iop)
 247     decoder_output = BasicConstructor.subst(iop)
 248     decode_block = BasicDecode.subst(iop)
 249     exec_output = BasicExecute.subst(iop)
 250 }};
 251
 252 def format FloatConvertOp(code, *flags) {{
 253     import sys
 254
 255     #Determine Source Type
 256     convert = 'fpConvert('
 257     if '_sf' in code:
 258         code = 'float ' + code + '\n'
 259         convert += 'SINGLE_TO_'
 260     elif '_df' in code:
 261         code = 'double ' + code + '\n'
 262         convert += 'DOUBLE_TO_'
 263     elif '_sw' in code:
 264         code = 'int32_t ' + code + '\n'
 265         convert += 'WORD_TO_'
 266     elif '_sd' in code:
 267         code = 'int64_t ' + code + '\n'
 268         convert += 'LONG_TO_'
 269     else:
 270         sys.exit("Error Determining Source Type for Conversion")
 271
 272     #Determine Destination Type
 273     if 'ToSingle' in flags:
 274         code += 'Fd_uw = ' + convert + 'SINGLE, '
 275     elif 'ToDouble' in flags:
 276         code += 'Fd_ud = ' + convert + 'DOUBLE, '
 277     elif 'ToWord' in flags:
 278         code += 'Fd_uw = ' + convert + 'WORD, '
 279     elif 'ToLong' in flags:
 280         code += 'Fd_ud = ' + convert + 'LONG, '
 281     else:
 282         sys.exit("Error Determining Destination Type for Conversion")
 283
 284     #Figure out how to round value
 285     if 'Ceil' in flags:
 286         code += 'ceil(val)); '
 287     elif 'Floor' in flags:
 288         code += 'floor(val)); '
 289     elif 'Round' in flags:
 290         code += 'roundFP(val, 0)); '
 291     elif 'Trunc' in flags:
 292         code += 'truncFP(val));'
 293     else:
 294         code += 'val); '
 295
 296     iop = InstObjParams(name, Name, 'FPOp', code)
 297     header_output = BasicDeclare.subst(iop)
 298     decoder_output = BasicConstructor.subst(iop)
 299     decode_block = BasicDecode.subst(iop)
 300     exec_output = BasicExecute.subst(iop)
 301 }};
 302
 303 def format FloatAccOp(code, *flags) {{
 304     iop = InstObjParams(name, Name, 'FPOp', code, flags)
 305     header_output = BasicDeclare.subst(iop)
 306     decoder_output = BasicConstructor.subst(iop)
 307     decode_block = BasicDecode.subst(iop)
 308     exec_output = BasicExecute.subst(iop)
 309 }};
 310
 311 // Primary format for float64 operate instructions:
 312 def format Float64Op(code, *flags) {{
 313     iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
 314     header_output = BasicDeclare.subst(iop)
 315     decoder_output = BasicConstructor.subst(iop)
 316     decode_block = BasicDecode.subst(iop)
 317     exec_output = BasicExecute.subst(iop)
 318 }};
 319
 320 def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
 321     import sys
 322
 323     code = 'bool cond1, cond2;\n'
 324     code += 'bool code_block1, code_block2;\n'
 325     code += 'code_block1 = code_block2 = true;\n'
 326
 327     if 'QnanException' in flags:
 328         code += 'if (isQnan(&Fs1_sf, 32) || isQnan(&Ft1_sf, 32)) {\n'
 329         code += '\tFCSR = genInvalidVector(FCSR);\n'
 330         code += 'code_block1 = false;'
 331         code += '}\n'
 332         code += 'if (isQnan(&Fs2_sf, 32) || isQnan(&Ft2_sf, 32)) {\n'
 333         code += '\tFCSR = genInvalidVector(FCSR);\n'
 334         code += 'code_block2 = false;'
 335         code += '}\n'
 336
 337     code += 'if (code_block1) {'
 338     code += '\tif (isNan(&Fs1_sf, 32) || isNan(&Ft1_sf, 32)) {\n'
 339     if 'UnorderedTrue' in flags:
 340        code += 'cond1 = 1;\n'
 341     elif 'UnorderedFalse' in flags:
 342        code += 'cond1 = 0;\n'
 343     else:
 344        sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
 345     code += '} else {\n'
 346     code +=  cond_code1
 347     code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
 348
 349     code += 'if (code_block2) {'
 350     code += '\tif (isNan(&Fs2_sf, 32) || isNan(&Ft2_sf, 32)) {\n'
 351     if 'UnorderedTrue' in flags:
 352        code += 'cond2 = 1;\n'
 353     elif 'UnorderedFalse' in flags:
 354        code += 'cond2 = 0;\n'
 355     else:
 356        sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
 357     code += '} else {\n'
 358     code +=  cond_code2
 359     code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
 360
 361     iop = InstObjParams(name, Name, 'FPCompareOp', code)
 362     header_output = BasicDeclare.subst(iop)
 363     decoder_output = BasicConstructor.subst(iop)
 364     decode_block = BasicDecode.subst(iop)
 365     exec_output = BasicExecute.subst(iop)
 366 }};
 367