src/arch/mips/isa/formats/fp.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2007 MIPS Technologies, Inc.
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 //
  29 // Authors: Korey Sewell
  30
  31 ////////////////////////////////////////////////////////////////////
  32 //
  33 // Floating Point operate instructions
  34 //
  35
  36 output header {{
  37         /**
  38          * Base class for FP operations.
  39          */
  40         class FPOp : public MipsStaticInst
  41         {
  42                 protected:
  43
  44                 /// Constructor
  45                 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
  46                 {
  47                 }
  48
  49                 //needs function to check for fpEnable or not
  50         };
  51
  52         class FPCompareOp : public FPOp
  53         {
  54           protected:
  55             FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
  56                 {
  57                 }
  58
  59             std::string generateDisassembly(
  60                     Addr pc, const SymbolTable *symtab) const override;
  61         };
  62 }};
  63
  64 output decoder {{
  65         std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
  66         {
  67             std::stringstream ss;
  68
  69             ccprintf(ss, "%-10s ", mnemonic);
  70
  71             ccprintf(ss,"%d",CC);
  72
  73             if(_numSrcRegs > 0) {
  74                 ss << ", ";
  75                 printReg(ss, _srcRegIdx[0]);
  76             }
  77
  78             if(_numSrcRegs > 1) {
  79                 ss << ", ";
  80                 printReg(ss, _srcRegIdx[1]);
  81             }
  82
  83             return ss.str();
  84         }
  85 }};
  86
  87 output header {{
  88         void fpResetCauseBits(ExecContext *cpu);
  89
  90 }};
  91
  92 output exec {{
  93         inline Fault checkFpEnableFault(ExecContext *xc)
  94         {
  95             //@TODO: Implement correct CP0 checks to see if the CP1
  96             // unit is enable or not
  97           if (!isCoprocessorEnabled(xc, 1))
  98               return std::make_shared<CoprocessorUnusableFault>(1);
  99
 100           return NoFault;
 101         }
 102
 103         //If any operand is Nan return the appropriate QNaN
 104         template <class T>
 105         bool
 106         fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type,
 107                       Trace::InstRecord *traceData)
 108         {
 109             uint64_t mips_nan = 0;
 110             assert(sizeof(T) == 4);
 111
 112             for (int i = 0; i < inst->numSrcRegs(); i++) {
 113                 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0);
 114
 115                 if (isNan(&src_bits, 32) ) {
 116                     mips_nan = MIPS32_QNAN;
 117                     xc->setFloatRegOperandBits(inst, 0, mips_nan);
 118                     if (traceData) { traceData->setData(mips_nan); }
 119                     return true;
 120                 }
 121             }
 122             return false;
 123         }
 124
 125         template <class T>
 126         bool
 127         fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val,
 128                     Trace::InstRecord *traceData)
 129         {
 130             uint64_t mips_nan = 0;
 131             T src_op = dest_val;
 132             assert(sizeof(T) == 4);
 133
 134             if (isNan(&src_op, 32)) {
 135                 mips_nan = MIPS32_QNAN;
 136
 137                 //Set value to QNAN
 138                 cpu->setFloatRegOperandBits(inst, 0, mips_nan);
 139
 140                 //Read FCSR from FloatRegFile
 141                 uint32_t fcsr_bits =
 142                     cpu->tcBase()->readFloatReg(FLOATREG_FCSR);
 143
 144                 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
 145
 146                 //Write FCSR from FloatRegFile
 147                 cpu->tcBase()->setFloatReg(FLOATREG_FCSR, new_fcsr);
 148
 149                 if (traceData) { traceData->setData(mips_nan); }
 150                 return true;
 151             }
 152
 153             return false;
 154         }
 155
 156         void
 157         fpResetCauseBits(ExecContext *cpu)
 158         {
 159             //Read FCSR from FloatRegFile
 160             uint32_t fcsr = cpu->tcBase()->readFloatReg(FLOATREG_FCSR);
 161
 162             // TODO: Use utility function here
 163             fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
 164
 165             //Write FCSR from FloatRegFile
 166             cpu->tcBase()->setFloatReg(FLOATREG_FCSR, fcsr);
 167         }
 168 }};
 169
 170 def template FloatingPointExecute {{
 171         Fault %(class_name)s::execute(
 172             ExecContext *xc, Trace::InstRecord *traceData) const
 173         {
 174                 Fault fault = NoFault;
 175
 176                 %(fp_enable_check)s;
 177
 178
 179                 //When is the right time to reset cause bits?
 180                 //start of every instruction or every cycle?
 181                 if (FullSystem)
 182                     fpResetCauseBits(xc);
 183                 %(op_decl)s;
 184                 %(op_rd)s;
 185
 186                 //Check if any FP operand is a NaN value
 187                 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
 188                     %(code)s;
 189
 190                     //Change this code for Full-System/Sycall Emulation
 191                     //separation
 192                     //----
 193                     //Should Full System-Mode throw a fault here?
 194                     //----
 195                     //Check for IEEE 754 FP Exceptions
 196                     //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
 197                     bool invalid_op = false;
 198                     if (FullSystem) {
 199                         invalid_op =
 200                             fpInvalidOp((FPOp*)this, xc, Fd, traceData);
 201                     }
 202                     if (!invalid_op && fault == NoFault) {
 203                         %(op_wb)s;
 204                     }
 205                 }
 206
 207                 return fault;
 208         }
 209 }};
 210
 211 // Primary format for float point operate instructions:
 212 def format FloatOp(code, *flags) {{
 213         iop = InstObjParams(name, Name, 'FPOp', code, flags)
 214         header_output = BasicDeclare.subst(iop)
 215         decoder_output = BasicConstructor.subst(iop)
 216         decode_block = BasicDecode.subst(iop)
 217         exec_output = FloatingPointExecute.subst(iop)
 218 }};
 219
 220 def format FloatCompareOp(cond_code, *flags) {{
 221     import sys
 222
 223     code = 'bool cond;\n'
 224     if '_sf' in cond_code or 'SinglePrecision' in flags:
 225         if 'QnanException' in flags:
 226             code += 'if (isQnan(&Fs_sf, 32) || isQnan(&Ft_sf, 32)) {\n'
 227             code += '\tFCSR = genInvalidVector(FCSR);\n'
 228             code += '\treturn NoFault;'
 229             code += '}\n else '
 230         code += 'if (isNan(&Fs_sf, 32) || isNan(&Ft_sf, 32)) {\n'
 231     elif '_df' in cond_code or 'DoublePrecision' in flags:
 232         if 'QnanException' in flags:
 233             code += 'if (isQnan(&Fs_df, 64) || isQnan(&Ft_df, 64)) {\n'
 234             code += '\tFCSR = genInvalidVector(FCSR);\n'
 235             code += '\treturn NoFault;'
 236             code += '}\n else '
 237         code += 'if (isNan(&Fs_df, 64) || isNan(&Ft_df, 64)) {\n'
 238     else:
 239        sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
 240
 241     if 'UnorderedTrue' in flags:
 242        code += 'cond = 1;\n'
 243     elif 'UnorderedFalse' in flags:
 244        code += 'cond = 0;\n'
 245     else:
 246        sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
 247
 248     code += '} else {\n'
 249     code +=  cond_code + '}'
 250     code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
 251
 252     iop = InstObjParams(name, Name, 'FPCompareOp', code)
 253     header_output = BasicDeclare.subst(iop)
 254     decoder_output = BasicConstructor.subst(iop)
 255     decode_block = BasicDecode.subst(iop)
 256     exec_output = BasicExecute.subst(iop)
 257 }};
 258
 259 def format FloatConvertOp(code, *flags) {{
 260     import sys
 261
 262     #Determine Source Type
 263     convert = 'fpConvert('
 264     if '_sf' in code:
 265         code = 'float ' + code + '\n'
 266         convert += 'SINGLE_TO_'
 267     elif '_df' in code:
 268         code = 'double ' + code + '\n'
 269         convert += 'DOUBLE_TO_'
 270     elif '_sw' in code:
 271         code = 'int32_t ' + code + '\n'
 272         convert += 'WORD_TO_'
 273     elif '_sd' in code:
 274         code = 'int64_t ' + code + '\n'
 275         convert += 'LONG_TO_'
 276     else:
 277         sys.exit("Error Determining Source Type for Conversion")
 278
 279     #Determine Destination Type
 280     if 'ToSingle' in flags:
 281         code += 'Fd_uw = ' + convert + 'SINGLE, '
 282     elif 'ToDouble' in flags:
 283         code += 'Fd_ud = ' + convert + 'DOUBLE, '
 284     elif 'ToWord' in flags:
 285         code += 'Fd_uw = ' + convert + 'WORD, '
 286     elif 'ToLong' in flags:
 287         code += 'Fd_ud = ' + convert + 'LONG, '
 288     else:
 289         sys.exit("Error Determining Destination Type for Conversion")
 290
 291     #Figure out how to round value
 292     if 'Ceil' in flags:
 293         code += 'ceil(val)); '
 294     elif 'Floor' in flags:
 295         code += 'floor(val)); '
 296     elif 'Round' in flags:
 297         code += 'roundFP(val, 0)); '
 298     elif 'Trunc' in flags:
 299         code += 'truncFP(val));'
 300     else:
 301         code += 'val); '
 302
 303     iop = InstObjParams(name, Name, 'FPOp', code)
 304     header_output = BasicDeclare.subst(iop)
 305     decoder_output = BasicConstructor.subst(iop)
 306     decode_block = BasicDecode.subst(iop)
 307     exec_output = BasicExecute.subst(iop)
 308 }};
 309
 310 def format FloatAccOp(code, *flags) {{
 311         iop = InstObjParams(name, Name, 'FPOp', code, flags)
 312         header_output = BasicDeclare.subst(iop)
 313         decoder_output = BasicConstructor.subst(iop)
 314         decode_block = BasicDecode.subst(iop)
 315         exec_output = BasicExecute.subst(iop)
 316 }};
 317
 318 // Primary format for float64 operate instructions:
 319 def format Float64Op(code, *flags) {{
 320         iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
 321         header_output = BasicDeclare.subst(iop)
 322         decoder_output = BasicConstructor.subst(iop)
 323         decode_block = BasicDecode.subst(iop)
 324         exec_output = BasicExecute.subst(iop)
 325 }};
 326
 327 def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
 328     import sys
 329
 330     code = 'bool cond1, cond2;\n'
 331     code += 'bool code_block1, code_block2;\n'
 332     code += 'code_block1 = code_block2 = true;\n'
 333
 334     if 'QnanException' in flags:
 335         code += 'if (isQnan(&Fs1_sf, 32) || isQnan(&Ft1_sf, 32)) {\n'
 336         code += '\tFCSR = genInvalidVector(FCSR);\n'
 337         code += 'code_block1 = false;'
 338         code += '}\n'
 339         code += 'if (isQnan(&Fs2_sf, 32) || isQnan(&Ft2_sf, 32)) {\n'
 340         code += '\tFCSR = genInvalidVector(FCSR);\n'
 341         code += 'code_block2 = false;'
 342         code += '}\n'
 343
 344     code += 'if (code_block1) {'
 345     code += '\tif (isNan(&Fs1_sf, 32) || isNan(&Ft1_sf, 32)) {\n'
 346     if 'UnorderedTrue' in flags:
 347        code += 'cond1 = 1;\n'
 348     elif 'UnorderedFalse' in flags:
 349        code += 'cond1 = 0;\n'
 350     else:
 351        sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
 352     code += '} else {\n'
 353     code +=  cond_code1
 354     code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
 355
 356     code += 'if (code_block2) {'
 357     code += '\tif (isNan(&Fs2_sf, 32) || isNan(&Ft2_sf, 32)) {\n'
 358     if 'UnorderedTrue' in flags:
 359        code += 'cond2 = 1;\n'
 360     elif 'UnorderedFalse' in flags:
 361        code += 'cond2 = 0;\n'
 362     else:
 363        sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
 364     code += '} else {\n'
 365     code +=  cond_code2
 366     code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
 367
 368     iop = InstObjParams(name, Name, 'FPCompareOp', code)
 369     header_output = BasicDeclare.subst(iop)
 370     decoder_output = BasicConstructor.subst(iop)
 371     decode_block = BasicDecode.subst(iop)
 372     exec_output = BasicExecute.subst(iop)
 373 }};
 374