3 // Copyright (c) 2006 The Regents of The University of Michigan
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Korey Sewell
31 ////////////////////////////////////////////////////////////////////
33 // Floating Point operate instructions
38 * Base class for FP operations.
40 class FPOp : public MipsStaticInst
45 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
49 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
51 //needs function to check for fpEnable or not
54 class FPCompareOp : public FPOp
57 FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
61 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
67 std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
71 ccprintf(ss, "%-10s ", mnemonic);
77 printReg(ss, _srcRegIdx[0]);
82 printReg(ss, _srcRegIdx[1]);
91 //If any operand is Nan return the appropriate QNaN
94 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
95 Trace::InstRecord *traceData)
97 uint64_t mips_nan = 0;
99 int size = sizeof(src_op) * 8;
101 for (int i = 0; i < inst->numSrcRegs(); i++) {
102 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
104 if (isNan(&src_bits, size) ) {
105 if (isSnan(&src_bits, size)) {
108 case 32: mips_nan = MIPS32_QNAN; break;
109 case 64: mips_nan = MIPS64_QNAN; break;
110 default: panic("Unsupported Floating Point Size (%d)", size);
116 xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
117 if (traceData) { traceData->setData(mips_nan); }
126 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
127 Trace::InstRecord *traceData)
129 uint64_t mips_nan = 0;
131 int size = sizeof(src_op) * 8;
133 if (isNan(&src_op, size)) {
136 case 32: mips_nan = MIPS32_QNAN; break;
137 case 64: mips_nan = MIPS64_QNAN; break;
138 default: panic("Unsupported Floating Point Size (%d)", size);
142 cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
144 //Read FCSR from FloatRegFile
145 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
147 //Write FCSR from FloatRegFile
148 cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
150 if (traceData) { traceData->setData(mips_nan); }
158 fpResetCauseBits(%(CPU_exec_context)s *cpu)
160 //Read FCSR from FloatRegFile
161 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
163 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
165 //Write FCSR from FloatRegFile
166 cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
170 def template FloatingPointExecute {{
171 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
173 Fault fault = NoFault;
177 //When is the right time to reset cause bits?
178 //start of every instruction or every cycle?
180 fpResetCauseBits(xc);
185 //Check if any FP operand is a NaN value
186 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
189 //Change this code for Full-System/Sycall Emulation
192 //Should Full System-Mode throw a fault here?
194 //Check for IEEE 754 FP Exceptions
195 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
198 !fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
210 // Primary format for float point operate instructions:
211 def format FloatOp(code, *flags) {{
212 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
213 header_output = BasicDeclare.subst(iop)
214 decoder_output = BasicConstructor.subst(iop)
215 decode_block = BasicDecode.subst(iop)
216 exec_output = FloatingPointExecute.subst(iop)
219 def format FloatCompareOp(cond_code, *flags) {{
222 code = 'bool cond;\n'
223 if '.sf' in cond_code or 'SinglePrecision' in flags:
224 if 'QnanException' in flags:
225 code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n'
226 code += '\tFCSR = genInvalidVector(FCSR);\n'
227 code += '\treturn NoFault;'
229 code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n'
230 elif '.df' in cond_code or 'DoublePrecision' in flags:
231 if 'QnanException' in flags:
232 code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n'
233 code += '\tFCSR = genInvalidVector(FCSR);\n'
234 code += '\treturn NoFault;'
236 code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n'
238 sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
240 if 'UnorderedTrue' in flags:
241 code += 'cond = 1;\n'
242 elif 'UnorderedFalse' in flags:
243 code += 'cond = 0;\n'
245 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
248 code += cond_code + '}'
249 code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
251 iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
252 header_output = BasicDeclare.subst(iop)
253 decoder_output = BasicConstructor.subst(iop)
254 decode_block = BasicDecode.subst(iop)
255 exec_output = BasicExecute.subst(iop)
258 def format FloatConvertOp(code, *flags) {{
261 #Determine Source Type
262 convert = 'fpConvert('
264 code = 'float ' + code + '\n'
265 convert += 'SINGLE_TO_'
267 code = 'double ' + code + '\n'
268 convert += 'DOUBLE_TO_'
270 code = 'uint32_t ' + code + '\n'
271 convert += 'WORD_TO_'
273 code = 'uint64_t ' + code + '\n'
274 convert += 'LONG_TO_'
276 sys.exit("Error Determining Source Type for Conversion")
278 #Determine Destination Type
279 if 'ToSingle' in flags:
280 code += 'Fd.uw = ' + convert + 'SINGLE, '
281 elif 'ToDouble' in flags:
282 code += 'Fd.ud = ' + convert + 'DOUBLE, '
283 elif 'ToWord' in flags:
284 code += 'Fd.uw = ' + convert + 'WORD, '
285 elif 'ToLong' in flags:
286 code += 'Fd.ud = ' + convert + 'LONG, '
288 sys.exit("Error Determining Destination Type for Conversion")
290 #Figure out how to round value
292 code += 'ceil(val)); '
293 elif 'Floor' in flags:
294 code += 'floor(val)); '
295 elif 'Round' in flags:
296 code += 'roundFP(val, 0)); '
297 elif 'Trunc' in flags:
298 code += 'truncFP(val));'
302 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code))
303 header_output = BasicDeclare.subst(iop)
304 decoder_output = BasicConstructor.subst(iop)
305 decode_block = BasicDecode.subst(iop)
306 exec_output = BasicExecute.subst(iop)
309 def format FloatAccOp(code, *flags) {{
310 iop = InstObjParams(name, Name, 'FPOp', CodeBlock(code), flags)
311 header_output = BasicDeclare.subst(iop)
312 decoder_output = BasicConstructor.subst(iop)
313 decode_block = BasicDecode.subst(iop)
314 exec_output = BasicExecute.subst(iop)
317 // Primary format for float64 operate instructions:
318 def format Float64Op(code, *flags) {{
319 iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
320 header_output = BasicDeclare.subst(iop)
321 decoder_output = BasicConstructor.subst(iop)
322 decode_block = BasicDecode.subst(iop)
323 exec_output = BasicExecute.subst(iop)
326 def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
329 code = 'bool cond1, cond2;\n'
330 code += 'bool code_block1, code_block2;\n'
331 code += 'code_block1 = code_block2 = true;\n'
333 if 'QnanException' in flags:
334 code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n'
335 code += '\tFCSR = genInvalidVector(FCSR);\n'
336 code += 'code_block1 = false;'
338 code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n'
339 code += '\tFCSR = genInvalidVector(FCSR);\n'
340 code += 'code_block2 = false;'
343 code += 'if (code_block1) {'
344 code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n'
345 if 'UnorderedTrue' in flags:
346 code += 'cond1 = 1;\n'
347 elif 'UnorderedFalse' in flags:
348 code += 'cond1 = 0;\n'
350 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
353 code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
355 code += 'if (code_block2) {'
356 code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n'
357 if 'UnorderedTrue' in flags:
358 code += 'cond2 = 1;\n'
359 elif 'UnorderedFalse' in flags:
360 code += 'cond2 = 0;\n'
362 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
365 code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
367 iop = InstObjParams(name, Name, 'FPCompareOp', CodeBlock(code))
368 header_output = BasicDeclare.subst(iop)
369 decoder_output = BasicConstructor.subst(iop)
370 decode_block = BasicDecode.subst(iop)
371 exec_output = BasicExecute.subst(iop)