3 // Copyright (c) 2007 MIPS Technologies, Inc.
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Korey Sewell
31 ////////////////////////////////////////////////////////////////////
33 // Floating Point operate instructions
38 * Base class for FP operations.
40 class FPOp : public MipsStaticInst
45 FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
49 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
51 //needs function to check for fpEnable or not
54 class FPCompareOp : public FPOp
57 FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
61 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
67 std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
71 ccprintf(ss, "%-10s ", mnemonic);
77 printReg(ss, _srcRegIdx[0]);
82 printReg(ss, _srcRegIdx[1]);
90 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
92 //@TODO: Implement correct CP0 checks to see if the CP1
93 // unit is enable or not
94 if (!isCoprocessorEnabled(xc, 1))
95 return new CoprocessorUnusableFault(1);
100 //If any operand is Nan return the appropriate QNaN
103 fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
104 Trace::InstRecord *traceData)
106 uint64_t mips_nan = 0;
107 assert(sizeof(T) == 4);
109 for (int i = 0; i < inst->numSrcRegs(); i++) {
110 uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0);
112 if (isNan(&src_bits, 32) ) {
113 mips_nan = MIPS32_QNAN;
114 xc->setFloatRegOperandBits(inst, 0, mips_nan);
115 if (traceData) { traceData->setData(mips_nan); }
124 fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
125 Trace::InstRecord *traceData)
127 uint64_t mips_nan = 0;
129 assert(sizeof(T) == 4);
131 if (isNan(&src_op, 32)) {
132 mips_nan = MIPS32_QNAN;
135 cpu->setFloatRegOperandBits(inst, 0, mips_nan);
137 //Read FCSR from FloatRegFile
139 cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
141 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
143 //Write FCSR from FloatRegFile
144 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr);
146 if (traceData) { traceData->setData(mips_nan); }
154 fpResetCauseBits(%(CPU_exec_context)s *cpu)
156 //Read FCSR from FloatRegFile
157 uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
159 // TODO: Use utility function here
160 fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
162 //Write FCSR from FloatRegFile
163 cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr);
167 def template FloatingPointExecute {{
168 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
170 Fault fault = NoFault;
175 //When is the right time to reset cause bits?
176 //start of every instruction or every cycle?
178 fpResetCauseBits(xc);
182 //Check if any FP operand is a NaN value
183 if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
186 //Change this code for Full-System/Sycall Emulation
189 //Should Full System-Mode throw a fault here?
191 //Check for IEEE 754 FP Exceptions
192 //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
193 bool invalid_op = false;
196 fpInvalidOp((FPOp*)this, xc, Fd, traceData);
198 if (!invalid_op && fault == NoFault) {
207 // Primary format for float point operate instructions:
208 def format FloatOp(code, *flags) {{
209 iop = InstObjParams(name, Name, 'FPOp', code, flags)
210 header_output = BasicDeclare.subst(iop)
211 decoder_output = BasicConstructor.subst(iop)
212 decode_block = BasicDecode.subst(iop)
213 exec_output = FloatingPointExecute.subst(iop)
216 def format FloatCompareOp(cond_code, *flags) {{
219 code = 'bool cond;\n'
220 if '_sf' in cond_code or 'SinglePrecision' in flags:
221 if 'QnanException' in flags:
222 code += 'if (isQnan(&Fs_sf, 32) || isQnan(&Ft_sf, 32)) {\n'
223 code += '\tFCSR = genInvalidVector(FCSR);\n'
224 code += '\treturn NoFault;'
226 code += 'if (isNan(&Fs_sf, 32) || isNan(&Ft_sf, 32)) {\n'
227 elif '_df' in cond_code or 'DoublePrecision' in flags:
228 if 'QnanException' in flags:
229 code += 'if (isQnan(&Fs_df, 64) || isQnan(&Ft_df, 64)) {\n'
230 code += '\tFCSR = genInvalidVector(FCSR);\n'
231 code += '\treturn NoFault;'
233 code += 'if (isNan(&Fs_df, 64) || isNan(&Ft_df, 64)) {\n'
235 sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
237 if 'UnorderedTrue' in flags:
238 code += 'cond = 1;\n'
239 elif 'UnorderedFalse' in flags:
240 code += 'cond = 0;\n'
242 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
245 code += cond_code + '}'
246 code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
248 iop = InstObjParams(name, Name, 'FPCompareOp', code)
249 header_output = BasicDeclare.subst(iop)
250 decoder_output = BasicConstructor.subst(iop)
251 decode_block = BasicDecode.subst(iop)
252 exec_output = BasicExecute.subst(iop)
255 def format FloatConvertOp(code, *flags) {{
258 #Determine Source Type
259 convert = 'fpConvert('
261 code = 'float ' + code + '\n'
262 convert += 'SINGLE_TO_'
264 code = 'double ' + code + '\n'
265 convert += 'DOUBLE_TO_'
267 code = 'uint32_t ' + code + '\n'
268 convert += 'WORD_TO_'
270 code = 'uint64_t ' + code + '\n'
271 convert += 'LONG_TO_'
273 sys.exit("Error Determining Source Type for Conversion")
275 #Determine Destination Type
276 if 'ToSingle' in flags:
277 code += 'Fd_uw = ' + convert + 'SINGLE, '
278 elif 'ToDouble' in flags:
279 code += 'Fd_ud = ' + convert + 'DOUBLE, '
280 elif 'ToWord' in flags:
281 code += 'Fd_uw = ' + convert + 'WORD, '
282 elif 'ToLong' in flags:
283 code += 'Fd_ud = ' + convert + 'LONG, '
285 sys.exit("Error Determining Destination Type for Conversion")
287 #Figure out how to round value
289 code += 'ceil(val)); '
290 elif 'Floor' in flags:
291 code += 'floor(val)); '
292 elif 'Round' in flags:
293 code += 'roundFP(val, 0)); '
294 elif 'Trunc' in flags:
295 code += 'truncFP(val));'
299 iop = InstObjParams(name, Name, 'FPOp', code)
300 header_output = BasicDeclare.subst(iop)
301 decoder_output = BasicConstructor.subst(iop)
302 decode_block = BasicDecode.subst(iop)
303 exec_output = BasicExecute.subst(iop)
306 def format FloatAccOp(code, *flags) {{
307 iop = InstObjParams(name, Name, 'FPOp', code, flags)
308 header_output = BasicDeclare.subst(iop)
309 decoder_output = BasicConstructor.subst(iop)
310 decode_block = BasicDecode.subst(iop)
311 exec_output = BasicExecute.subst(iop)
314 // Primary format for float64 operate instructions:
315 def format Float64Op(code, *flags) {{
316 iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
317 header_output = BasicDeclare.subst(iop)
318 decoder_output = BasicConstructor.subst(iop)
319 decode_block = BasicDecode.subst(iop)
320 exec_output = BasicExecute.subst(iop)
323 def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
326 code = 'bool cond1, cond2;\n'
327 code += 'bool code_block1, code_block2;\n'
328 code += 'code_block1 = code_block2 = true;\n'
330 if 'QnanException' in flags:
331 code += 'if (isQnan(&Fs1_sf, 32) || isQnan(&Ft1_sf, 32)) {\n'
332 code += '\tFCSR = genInvalidVector(FCSR);\n'
333 code += 'code_block1 = false;'
335 code += 'if (isQnan(&Fs2_sf, 32) || isQnan(&Ft2_sf, 32)) {\n'
336 code += '\tFCSR = genInvalidVector(FCSR);\n'
337 code += 'code_block2 = false;'
340 code += 'if (code_block1) {'
341 code += '\tif (isNan(&Fs1_sf, 32) || isNan(&Ft1_sf, 32)) {\n'
342 if 'UnorderedTrue' in flags:
343 code += 'cond1 = 1;\n'
344 elif 'UnorderedFalse' in flags:
345 code += 'cond1 = 0;\n'
347 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
350 code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
352 code += 'if (code_block2) {'
353 code += '\tif (isNan(&Fs2_sf, 32) || isNan(&Ft2_sf, 32)) {\n'
354 if 'UnorderedTrue' in flags:
355 code += 'cond2 = 1;\n'
356 elif 'UnorderedFalse' in flags:
357 code += 'cond2 = 0;\n'
359 sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
362 code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
364 iop = InstObjParams(name, Name, 'FPCompareOp', code)
365 header_output = BasicDeclare.subst(iop)
366 decoder_output = BasicConstructor.subst(iop)
367 decode_block = BasicDecode.subst(iop)
368 exec_output = BasicExecute.subst(iop)