src/arch/mips/isa/formats/int.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2006 The Regents of The University of Michigan
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
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   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
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  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 //
  29 // Authors: Korey Sewell
  30
  31 ////////////////////////////////////////////////////////////////////
  32 //
  33 // Integer operate instructions
  34 //
  35 output header {{
  36 #include <iostream>
  37     using namespace std;
  38         /**
  39          * Base class for integer operations.
  40          */
  41         class IntOp : public MipsStaticInst
  42         {
  43                 protected:
  44
  45                 /// Constructor
  46                 IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
  47                                 MipsStaticInst(mnem, _machInst, __opClass)
  48                 {
  49                 }
  50
  51                 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
  52         };
  53
  54
  55         class HiLoOp: public IntOp
  56         {
  57                 protected:
  58
  59                 /// Constructor
  60                 HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
  61                                 IntOp(mnem, _machInst, __opClass)
  62                 {
  63                 }
  64
  65                 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
  66         };
  67
  68         class HiLoMiscOp: public HiLoOp
  69         {
  70                 protected:
  71
  72                 /// Constructor
  73                 HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
  74                                 HiLoOp(mnem, _machInst, __opClass)
  75                 {
  76                 }
  77
  78                 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
  79         };
  80
  81
  82         class IntImmOp : public MipsStaticInst
  83         {
  84                 protected:
  85
  86                 int16_t imm;
  87                 int32_t sextImm;
  88                 uint32_t zextImm;
  89
  90                 /// Constructor
  91                 IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
  92                     MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
  93                     sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
  94                 {
  95                     //If Bit 15 is 1 then Sign Extend
  96                     int32_t temp = sextImm & 0x00008000;
  97                     if (temp > 0 && mnemonic != "lui") {
  98                         sextImm |= 0xFFFF0000;
  99                     }
 100                 }
 101
 102                 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 103
 104
 105         };
 106
 107 }};
 108
 109 // HiLo<Misc> instruction class execute method template.
 110 // Mainly to get instruction trace data to print out
 111 // correctly
 112 def template HiLoExecute {{
 113         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
 114         {
 115                 Fault fault = NoFault;
 116
 117                 %(fp_enable_check)s;
 118                 %(op_decl)s;
 119                 %(op_rd)s;
 120                 %(code)s;
 121
 122                 if(fault == NoFault)
 123                 {
 124                     %(op_wb)s;
 125                     //If there are 2 Destination Registers then
 126                     //concatenate the values for the traceData
 127                     if(traceData && _numDestRegs == 2) {
 128                         uint64_t hilo_final_val = (uint64_t)HI << 32 | LO;
 129                         traceData->setData(hilo_final_val);
 130                     }
 131                 }
 132                 return fault;
 133         }
 134 }};
 135
 136 //Outputs to decoder.cc
 137 output decoder {{
 138         std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 139         {
 140             std::stringstream ss;
 141
 142             ccprintf(ss, "%-10s ", mnemonic);
 143
 144             // just print the first dest... if there's a second one,
 145             // it's generally implicit
 146             if (_numDestRegs > 0) {
 147                 printReg(ss, _destRegIdx[0]);
 148                 ss << ", ";
 149             }
 150
 151             // just print the first two source regs... if there's
 152             // a third one, it's a read-modify-write dest (Rc),
 153             // e.g. for CMOVxx
 154             if (_numSrcRegs > 0) {
 155                 printReg(ss, _srcRegIdx[0]);
 156             }
 157
 158             if (_numSrcRegs > 1) {
 159                 ss << ", ";
 160                 printReg(ss, _srcRegIdx[1]);
 161             }
 162
 163             return ss.str();
 164         }
 165
 166         std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 167         {
 168             std::stringstream ss;
 169
 170             ccprintf(ss, "%-10s ", mnemonic);
 171
 172             //Destination Registers are implicit for HI/LO ops
 173             if (_numSrcRegs > 0) {
 174                 printReg(ss, _srcRegIdx[0]);
 175             }
 176
 177             if (_numSrcRegs > 1) {
 178                 ss << ", ";
 179                 printReg(ss, _srcRegIdx[1]);
 180             }
 181
 182             return ss.str();
 183         }
 184
 185         std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 186         {
 187             std::stringstream ss;
 188
 189             ccprintf(ss, "%-10s ", mnemonic);
 190
 191             if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
 192                 printReg(ss, _destRegIdx[0]);
 193             } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
 194                 printReg(ss, _srcRegIdx[0]);
 195             }
 196
 197             return ss.str();
 198         }
 199
 200         std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 201         {
 202             std::stringstream ss;
 203
 204             ccprintf(ss, "%-10s ", mnemonic);
 205
 206             if (_numDestRegs > 0) {
 207                 printReg(ss, _destRegIdx[0]);
 208             }
 209
 210             ss << ", ";
 211
 212             if (_numSrcRegs > 0) {
 213                 printReg(ss, _srcRegIdx[0]);
 214                 ss << ", ";
 215             }
 216
 217             if( mnemonic == "lui")
 218                 ccprintf(ss, "0x%x ", sextImm);
 219             else
 220                 ss << (int) sextImm;
 221
 222             return ss.str();
 223         }
 224
 225 }};
 226
 227 def format IntOp(code, *opt_flags) {{
 228     iop = InstObjParams(name, Name, 'IntOp', CodeBlock(code), opt_flags)
 229     header_output = BasicDeclare.subst(iop)
 230     decoder_output = BasicConstructor.subst(iop)
 231     decode_block = RegNopCheckDecode.subst(iop)
 232     exec_output = BasicExecute.subst(iop)
 233 }};
 234
 235 def format IntImmOp(code, *opt_flags) {{
 236     iop = InstObjParams(name, Name, 'IntImmOp', CodeBlock(code), opt_flags)
 237     header_output = BasicDeclare.subst(iop)
 238     decoder_output = BasicConstructor.subst(iop)
 239     decode_block = ImmNopCheckDecode.subst(iop)
 240     exec_output = BasicExecute.subst(iop)
 241 }};
 242
 243 def format HiLoOp(code, *opt_flags) {{
 244     if '.sd' in code:
 245         code = 'int64_t ' + code
 246     elif '.ud' in code:
 247         code = 'uint64_t ' + code
 248
 249     code += 'HI = val<63:32>;\n'
 250     code += 'LO = val<31:0>;\n'
 251
 252     iop = InstObjParams(name, Name, 'HiLoOp', CodeBlock(code), opt_flags)
 253     header_output = BasicDeclare.subst(iop)
 254     decoder_output = BasicConstructor.subst(iop)
 255     decode_block = BasicDecode.subst(iop)
 256     exec_output = HiLoExecute.subst(iop)
 257 }};
 258
 259 def format HiLoMiscOp(code, *opt_flags) {{
 260     iop = InstObjParams(name, Name, 'HiLoMiscOp', CodeBlock(code), opt_flags)
 261     header_output = BasicDeclare.subst(iop)
 262     decoder_output = BasicConstructor.subst(iop)
 263     decode_block = BasicDecode.subst(iop)
 264     exec_output = HiLoExecute.subst(iop)
 265 }};
 266
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 270