3 // Copyright (c) 2006 The Regents of The University of Michigan
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Steve Reinhardt
32 ////////////////////////////////////////////////////////////////////
34 // Memory-format instructions
39 * Base class for general Mips memory-format instructions.
41 class Memory : public MipsStaticInst
45 /// Memory request flags. See mem_req_base.hh.
46 unsigned memAccessFlags;
47 /// Pointer to EAComp object.
48 const StaticInstPtr eaCompPtr;
49 /// Pointer to MemAcc object.
50 const StaticInstPtr memAccPtr;
52 /// Displacement for EA calculation (signed).
56 Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
57 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
58 StaticInstPtr _memAccPtr = nullStaticInstPtr)
59 : MipsStaticInst(mnem, _machInst, __opClass),
60 memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
61 disp(sext<16>(OFFSET))
66 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
70 const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
71 const StaticInstPtr &memAccInst() const { return memAccPtr; }
75 * Base class for a few miscellaneous memory-format insts
76 * that don't interpret the disp field
78 class MemoryNoDisp : public Memory
82 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
83 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
84 StaticInstPtr _memAccPtr = nullStaticInstPtr)
85 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
90 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
97 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
99 return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
100 flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
104 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
106 return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
107 flags[IsFloating] ? 'f' : 'r',
108 flags[IsFloating] ? FD : RD,
113 def template LoadStoreDeclare {{
115 * Static instruction class for "%(mnemonic)s".
117 class %(class_name)s : public %(base_class)s
122 * "Fake" effective address computation class for "%(mnemonic)s".
124 class EAComp : public %(base_class)s
128 EAComp(MachInst machInst);
134 * "Fake" memory access instruction class for "%(mnemonic)s".
136 class MemAcc : public %(base_class)s
140 MemAcc(MachInst machInst);
148 %(class_name)s(MachInst machInst);
152 %(InitiateAccDeclare)s
154 %(CompleteAccDeclare)s
159 def template InitiateAccDeclare {{
160 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
164 def template CompleteAccDeclare {{
165 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
169 def template EACompConstructor {{
170 /** TODO: change op_class to AddrGenOp or something (requires
171 * creating new member of OpClass enum in op_class.hh, updating
172 * config files, etc.). */
173 inline %(class_name)s::EAComp::EAComp(MachInst machInst)
174 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
181 def template MemAccConstructor {{
182 inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
183 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
190 def template LoadStoreConstructor {{
191 inline %(class_name)s::%(class_name)s(MachInst machInst)
192 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
193 new EAComp(machInst), new MemAcc(machInst))
200 def template EACompExecute {{
202 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
203 Trace::InstRecord *traceData) const
206 Fault fault = NoFault;
213 if (fault == NoFault) {
222 def template LoadMemAccExecute {{
224 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
225 Trace::InstRecord *traceData) const
228 Fault fault = NoFault;
235 if (fault == NoFault) {
236 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
240 if (fault == NoFault) {
249 def template LoadExecute {{
250 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
251 Trace::InstRecord *traceData) const
254 Fault fault = NoFault;
261 if (fault == NoFault) {
262 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
266 if (fault == NoFault) {
275 def template LoadInitiateAcc {{
276 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
277 Trace::InstRecord *traceData) const
280 Fault fault = NoFault;
287 if (fault == NoFault) {
288 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
296 def template LoadCompleteAcc {{
297 Fault %(class_name)s::completeAcc(PacketPtr pkt,
298 %(CPU_exec_context)s *xc,
299 Trace::InstRecord *traceData) const
301 Fault fault = NoFault;
306 Mem = pkt->get<typeof(Mem)>();
308 if (fault == NoFault) {
312 if (fault == NoFault) {
321 def template StoreMemAccExecute {{
323 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
324 Trace::InstRecord *traceData) const
327 Fault fault = NoFault;
328 uint64_t write_result = 0;
335 if (fault == NoFault) {
339 if (fault == NoFault) {
340 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
341 memAccessFlags, &write_result);
342 if (traceData) { traceData->setData(Mem); }
345 if (fault == NoFault) {
349 if (fault == NoFault) {
358 def template StoreExecute {{
359 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
360 Trace::InstRecord *traceData) const
363 Fault fault = NoFault;
364 uint64_t write_result = 0;
371 if (fault == NoFault) {
375 if (fault == NoFault) {
376 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
377 memAccessFlags, &write_result);
378 if (traceData) { traceData->setData(Mem); }
381 if (fault == NoFault) {
385 if (fault == NoFault) {
393 def template StoreInitiateAcc {{
394 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
395 Trace::InstRecord *traceData) const
398 Fault fault = NoFault;
405 if (fault == NoFault) {
409 if (fault == NoFault) {
410 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
411 memAccessFlags, NULL);
412 if (traceData) { traceData->setData(Mem); }
420 def template StoreCompleteAcc {{
421 Fault %(class_name)s::completeAcc(PacketPtr pkt,
422 %(CPU_exec_context)s *xc,
423 Trace::InstRecord *traceData) const
425 Fault fault = NoFault;
430 if (fault == NoFault) {
434 if (fault == NoFault) {
442 def template StoreCondCompleteAcc {{
443 Fault %(class_name)s::completeAcc(PacketPtr pkt,
444 %(CPU_exec_context)s *xc,
445 Trace::InstRecord *traceData) const
447 Fault fault = NoFault;
452 uint64_t write_result = pkt->req->getScResult();
454 if (fault == NoFault) {
458 if (fault == NoFault) {
467 def template MiscMemAccExecute {{
468 Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
469 Trace::InstRecord *traceData) const
472 Fault fault = NoFault;
479 if (fault == NoFault) {
487 def template MiscExecute {{
488 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
489 Trace::InstRecord *traceData) const
492 Fault fault = NoFault;
499 if (fault == NoFault) {
507 def template MiscInitiateAcc {{
508 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
509 Trace::InstRecord *traceData) const
511 panic("Misc instruction does not support split access method!");
517 def template MiscCompleteAcc {{
518 Fault %(class_name)s::completeAcc(PacketPtr pkt,
519 %(CPU_exec_context)s *xc,
520 Trace::InstRecord *traceData) const
522 panic("Misc instruction does not support split access method!");
528 def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
529 mem_flags = [], inst_flags = []) {{
530 (header_output, decoder_output, decode_block, exec_output) = \
531 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
532 decode_template = ImmNopCheckDecode,
533 exec_template_base = 'Load')
536 def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
537 mem_flags = [], inst_flags = []) {{
538 (header_output, decoder_output, decode_block, exec_output) = \
539 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
540 exec_template_base = 'Store')
543 def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
544 mem_flags = [], inst_flags = []) {{
545 (header_output, decoder_output, decode_block, exec_output) = \
546 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
547 decode_template = ImmNopCheckDecode,
548 exec_template_base = 'Load')
551 def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
552 mem_flags = [], inst_flags = []) {{
553 (header_output, decoder_output, decode_block, exec_output) = \
554 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
555 exec_template_base = 'Store')
558 def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
559 mem_flags = [], inst_flags = []) {{
560 decl_code = 'uint32_t mem_word = Mem.uw;\n'
561 decl_code += 'uint32_t unalign_addr = Rs + disp;\n'
562 decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n'
563 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
564 decl_code += '\tbyte_offset ^= 3;\n'
565 decl_code += '#endif\n'
567 memacc_code = decl_code + memacc_code
569 (header_output, decoder_output, decode_block, exec_output) = \
570 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
571 decode_template = ImmNopCheckDecode,
572 exec_template_base = 'Load')
575 def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
576 mem_flags = [], inst_flags = []) {{
577 decl_code = 'uint32_t mem_word = 0;\n'
578 decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
579 decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
580 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
581 decl_code += '\tbyte_offset ^= 3;\n'
582 decl_code += '#endif\n'
583 decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
584 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
586 (header_output, decoder_output, decode_block, exec_output) = \
587 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
588 exec_template_base = 'Store')
591 def format Prefetch(ea_code = {{ EA = Rs + disp; }},
592 mem_flags = [], pf_flags = [], inst_flags = []) {{
593 pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
594 pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
595 'IsDataPrefetch', 'MemReadOp']
597 (header_output, decoder_output, decode_block, exec_output) = \
598 LoadStoreBase(name, Name, ea_code,
599 'xc->prefetch(EA, memAccessFlags);',
600 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
604 def format StoreCond(memacc_code, postacc_code,
605 ea_code = {{ EA = Rs + disp; }},
606 mem_flags = [], inst_flags = []) {{
607 (header_output, decoder_output, decode_block, exec_output) = \
608 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
609 postacc_code, exec_template_base = 'StoreCond')