3 // Copyright (c) 2006 The Regents of The University of Michigan
4 // All rights reserved.
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
12 // documentation and/or other materials provided with the distribution;
13 // neither the name of the copyright holders nor the names of its
14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 // Authors: Steve Reinhardt
32 ////////////////////////////////////////////////////////////////////
34 // Memory-format instructions
39 * Base class for general Mips memory-format instructions.
41 class Memory : public MipsStaticInst
45 /// Memory request flags. See mem_req_base.hh.
46 unsigned memAccessFlags;
47 /// Pointer to EAComp object.
48 const StaticInstPtr eaCompPtr;
49 /// Pointer to MemAcc object.
50 const StaticInstPtr memAccPtr;
52 /// Displacement for EA calculation (signed).
56 Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
57 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
58 StaticInstPtr _memAccPtr = nullStaticInstPtr)
59 : MipsStaticInst(mnem, _machInst, __opClass),
60 memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
61 disp(sext<16>(OFFSET))
66 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
70 const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
71 const StaticInstPtr &memAccInst() const { return memAccPtr; }
75 * Base class for a few miscellaneous memory-format insts
76 * that don't interpret the disp field
78 class MemoryNoDisp : public Memory
82 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
83 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
84 StaticInstPtr _memAccPtr = nullStaticInstPtr)
85 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
90 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
97 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
99 return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
100 flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
104 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
106 return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
107 flags[IsFloating] ? 'f' : 'r',
108 flags[IsFloating] ? FD : RD,
113 def template LoadStoreDeclare {{
115 * Static instruction class for "%(mnemonic)s".
117 class %(class_name)s : public %(base_class)s
122 * "Fake" effective address computation class for "%(mnemonic)s".
124 class EAComp : public %(base_class)s
128 EAComp(MachInst machInst);
134 * "Fake" memory access instruction class for "%(mnemonic)s".
136 class MemAcc : public %(base_class)s
140 MemAcc(MachInst machInst);
148 %(class_name)s(MachInst machInst);
152 %(InitiateAccDeclare)s
154 %(CompleteAccDeclare)s
159 def template InitiateAccDeclare {{
160 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
164 def template CompleteAccDeclare {{
165 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
169 def template LoadStoreConstructor {{
170 /** TODO: change op_class to AddrGenOp or something (requires
171 * creating new member of OpClass enum in op_class.hh, updating
172 * config files, etc.). */
173 inline %(class_name)s::EAComp::EAComp(MachInst machInst)
174 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
179 inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
180 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
182 %(memacc_constructor)s;
185 inline %(class_name)s::%(class_name)s(MachInst machInst)
186 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
187 new EAComp(machInst), new MemAcc(machInst))
194 def template EACompExecute {{
196 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
197 Trace::InstRecord *traceData) const
200 Fault fault = NoFault;
207 if (fault == NoFault) {
216 def template LoadMemAccExecute {{
218 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
219 Trace::InstRecord *traceData) const
222 Fault fault = NoFault;
229 if (fault == NoFault) {
230 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
234 if (fault == NoFault) {
243 def template LoadExecute {{
244 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
245 Trace::InstRecord *traceData) const
248 Fault fault = NoFault;
255 if (fault == NoFault) {
256 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
260 if (fault == NoFault) {
269 def template LoadInitiateAcc {{
270 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
271 Trace::InstRecord *traceData) const
274 Fault fault = NoFault;
281 if (fault == NoFault) {
282 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
290 def template LoadCompleteAcc {{
291 Fault %(class_name)s::completeAcc(PacketPtr pkt,
292 %(CPU_exec_context)s *xc,
293 Trace::InstRecord *traceData) const
295 Fault fault = NoFault;
300 Mem = pkt->get<typeof(Mem)>();
302 if (fault == NoFault) {
306 if (fault == NoFault) {
315 def template StoreMemAccExecute {{
317 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
318 Trace::InstRecord *traceData) const
321 Fault fault = NoFault;
322 uint64_t write_result = 0;
329 if (fault == NoFault) {
333 if (fault == NoFault) {
334 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
335 memAccessFlags, &write_result);
336 if (traceData) { traceData->setData(Mem); }
339 if (fault == NoFault) {
343 if (fault == NoFault) {
352 def template StoreExecute {{
353 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
354 Trace::InstRecord *traceData) const
357 Fault fault = NoFault;
358 uint64_t write_result = 0;
365 if (fault == NoFault) {
369 if (fault == NoFault) {
370 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
371 memAccessFlags, &write_result);
372 if (traceData) { traceData->setData(Mem); }
375 if (fault == NoFault) {
379 if (fault == NoFault) {
387 def template StoreInitiateAcc {{
388 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
389 Trace::InstRecord *traceData) const
392 Fault fault = NoFault;
399 if (fault == NoFault) {
403 if (fault == NoFault) {
404 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
405 memAccessFlags, NULL);
406 if (traceData) { traceData->setData(Mem); }
414 def template StoreCompleteAcc {{
415 Fault %(class_name)s::completeAcc(PacketPtr pkt,
416 %(CPU_exec_context)s *xc,
417 Trace::InstRecord *traceData) const
419 Fault fault = NoFault;
424 if (fault == NoFault) {
428 if (fault == NoFault) {
436 def template StoreCondCompleteAcc {{
437 Fault %(class_name)s::completeAcc(PacketPtr pkt,
438 %(CPU_exec_context)s *xc,
439 Trace::InstRecord *traceData) const
441 Fault fault = NoFault;
446 uint64_t write_result = pkt->req->getScResult();
448 if (fault == NoFault) {
452 if (fault == NoFault) {
461 def template MiscMemAccExecute {{
462 Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
463 Trace::InstRecord *traceData) const
466 Fault fault = NoFault;
473 if (fault == NoFault) {
481 def template MiscExecute {{
482 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
483 Trace::InstRecord *traceData) const
486 Fault fault = NoFault;
493 if (fault == NoFault) {
501 def template MiscInitiateAcc {{
502 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
503 Trace::InstRecord *traceData) const
505 panic("Misc instruction does not support split access method!");
511 def template MiscCompleteAcc {{
512 Fault %(class_name)s::completeAcc(PacketPtr pkt,
513 %(CPU_exec_context)s *xc,
514 Trace::InstRecord *traceData) const
516 panic("Misc instruction does not support split access method!");
522 def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
523 mem_flags = [], inst_flags = []) {{
524 (header_output, decoder_output, decode_block, exec_output) = \
525 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
526 decode_template = ImmNopCheckDecode,
527 exec_template_base = 'Load')
530 def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
531 mem_flags = [], inst_flags = []) {{
532 (header_output, decoder_output, decode_block, exec_output) = \
533 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
534 exec_template_base = 'Store')
537 def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
538 mem_flags = [], inst_flags = []) {{
539 (header_output, decoder_output, decode_block, exec_output) = \
540 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
541 decode_template = ImmNopCheckDecode,
542 exec_template_base = 'Load')
545 def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
546 mem_flags = [], inst_flags = []) {{
547 (header_output, decoder_output, decode_block, exec_output) = \
548 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
549 exec_template_base = 'Store')
552 def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
553 mem_flags = [], inst_flags = []) {{
554 decl_code = 'uint32_t mem_word = Mem.uw;\n'
555 decl_code += 'uint32_t unalign_addr = Rs + disp;\n'
556 decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n'
557 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
558 decl_code += '\tbyte_offset ^= 3;\n'
559 decl_code += '#endif\n'
561 memacc_code = decl_code + memacc_code
563 (header_output, decoder_output, decode_block, exec_output) = \
564 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
565 decode_template = ImmNopCheckDecode,
566 exec_template_base = 'Load')
569 def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
570 mem_flags = [], inst_flags = []) {{
571 decl_code = 'uint32_t mem_word = 0;\n'
572 decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
573 decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
574 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
575 decl_code += '\tbyte_offset ^= 3;\n'
576 decl_code += '#endif\n'
577 decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
578 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
580 (header_output, decoder_output, decode_block, exec_output) = \
581 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
582 exec_template_base = 'Store')
585 def format Prefetch(ea_code = {{ EA = Rs + disp; }},
586 mem_flags = [], pf_flags = [], inst_flags = []) {{
587 pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
588 pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
589 'IsDataPrefetch', 'MemReadOp']
591 (header_output, decoder_output, decode_block, exec_output) = \
592 LoadStoreBase(name, Name, ea_code,
593 'xc->prefetch(EA, memAccessFlags);',
594 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
598 def format StoreCond(memacc_code, postacc_code,
599 ea_code = {{ EA = Rs + disp; }},
600 mem_flags = [], inst_flags = []) {{
601 (header_output, decoder_output, decode_block, exec_output) = \
602 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
603 postacc_code, exec_template_base = 'StoreCond')