src/arch/mips/isa/formats/mt.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2007 MIPS Technologies, Inc.
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 ////////////////////////////////////////////////////////////////////
  30 //
  31 // MT instructions
  32 //
  33
  34 output header {{
  35         /**
  36          * Base class for MIPS MT ASE operations.
  37          */
  38         class MTOp : public MipsStaticInst
  39         {
  40                 protected:
  41
  42                 /// Constructor
  43                 MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
  44                     MipsStaticInst(mnem, _machInst, __opClass), user_mode(false)
  45                 {
  46                 }
  47
  48                std::string generateDisassembly(
  49                        Addr pc, const SymbolTable *symtab) const override;
  50
  51                 bool user_mode;
  52         };
  53
  54         class MTUserModeOp : public MTOp
  55         {
  56                 protected:
  57
  58                 /// Constructor
  59                 MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
  60                     MTOp(mnem, _machInst, __opClass)
  61                 {
  62                     user_mode = true;
  63                 }
  64         };
  65 }};
  66
  67 output decoder {{
  68     std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
  69     {
  70         std::stringstream ss;
  71
  72         if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) {
  73             ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
  74         } else if (strcmp(mnemonic,"mftgpr") == 0) {
  75             ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
  76         } else {
  77             ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
  78         }
  79
  80         return ss.str();
  81     }
  82 }};
  83
  84 output header {{
  85    void getThrRegExValues(ExecContext *xc,
  86                           MipsISA::VPEConf0Reg &vpe_conf0,
  87                           MipsISA::TCBindReg &tc_bind_mt,
  88                           MipsISA::TCBindReg &tc_bind,
  89                           MipsISA::VPEControlReg &vpe_control,
  90                           MipsISA::MVPConf0Reg &mvp_conf0);
  91
  92    void getMTExValues(ExecContext *xc, MipsISA::Config3Reg &config3);
  93 }};
  94
  95 output exec {{
  96     void getThrRegExValues(ExecContext *xc,
  97             VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt,
  98             TCBindReg &tc_bind, VPEControlReg &vpe_control,
  99             MVPConf0Reg &mvp_conf0)
 100     {
 101         vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
 102         tc_bind_mt = readRegOtherThread(xc, RegId(MiscRegClass,
 103                                                   MISCREG_TC_BIND));
 104         tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
 105         vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
 106         mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
 107     }
 108
 109     void getMTExValues(ExecContext *xc, Config3Reg &config3)
 110     {
 111         config3 = xc->readMiscReg(MISCREG_CONFIG3);
 112     }
 113 }};
 114
 115 def template ThreadRegisterExecute {{
 116         Fault %(class_name)s::execute(
 117             ExecContext *xc, Trace::InstRecord *traceData) const
 118         {
 119             Fault fault = NoFault;
 120             int64_t data M5_VAR_USED;
 121             %(op_decl)s;
 122             %(op_rd)s;
 123
 124             VPEConf0Reg vpeConf0;
 125             TCBindReg tcBindMT;
 126             TCBindReg tcBind;
 127             VPEControlReg vpeControl;
 128             MVPConf0Reg mvpConf0;
 129
 130             getThrRegExValues(xc, vpeConf0, tcBindMT,
 131                                   tcBind, vpeControl, mvpConf0);
 132
 133             if (isCoprocessorEnabled(xc, 0)) {
 134                 if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) {
 135                     data = -1;
 136                 } else if (vpeControl.targTC > mvpConf0.ptc) {
 137                     data = -1;
 138                 } else {
 139                     %(code)s;
 140                 }
 141             } else {
 142                 fault = std::make_shared<CoprocessorUnusableFault>(0);
 143             }
 144
 145             if(fault == NoFault)
 146             {
 147                 %(op_wb)s;
 148             }
 149
 150             return fault;
 151         }
 152 }};
 153
 154 def template MTExecute{{
 155         Fault %(class_name)s::execute(
 156             ExecContext *xc, Trace::InstRecord *traceData) const
 157         {
 158                 Fault fault = NoFault;
 159                 %(op_decl)s;
 160                 %(op_rd)s;
 161
 162                 Config3Reg config3;
 163
 164                 getMTExValues(xc, config3);
 165
 166                 if (isCoprocessorEnabled(xc, 0)) {
 167                     if (config3.mt == 1) {
 168                         %(code)s;
 169                     } else {
 170                         fault = std::make_shared<ReservedInstructionFault>();
 171                     }
 172                 } else {
 173                     fault = std::make_shared<CoprocessorUnusableFault>(0);
 174                 }
 175
 176                 if(fault == NoFault)
 177                 {
 178                     %(op_wb)s;
 179                 }
 180                 return fault;
 181         }
 182 }};
 183
 184 // Primary format for integer operate instructions:
 185 def format MT_Control(code, *opt_flags) {{
 186         inst_flags = ('IsNonSpeculative', )
 187         op_type = 'MTOp'
 188
 189         for x in opt_flags:
 190             if x == 'UserMode':
 191                 op_type = 'MTUserModeOp'
 192             else:
 193                 inst_flags += (x, )
 194
 195         iop = InstObjParams(name, Name, op_type, code, inst_flags)
 196         header_output = BasicDeclare.subst(iop)
 197         decoder_output = BasicConstructor.subst(iop)
 198         decode_block = BasicDecode.subst(iop)
 199         exec_output = MTExecute.subst(iop)
 200 }};
 201
 202 def format MT_MFTR(code, *flags) {{
 203         flags += ('IsNonSpeculative', )
 204 #        code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
 205
 206         code += '''
 207             if (MT_H)
 208                 data = bits(data, 63, 32);
 209             Rd = data;
 210         '''
 211
 212         iop = InstObjParams(name, Name, 'MTOp', code, flags)
 213         header_output = BasicDeclare.subst(iop)
 214         decoder_output = BasicConstructor.subst(iop)
 215         decode_block = BasicDecode.subst(iop)
 216         exec_output = ThreadRegisterExecute.subst(iop)
 217 }};
 218
 219 def format MT_MTTR(code, *flags) {{
 220         flags += ('IsNonSpeculative', )
 221 #        code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
 222         iop = InstObjParams(name, Name, 'MTOp', code, flags)
 223         header_output = BasicDeclare.subst(iop)
 224         decoder_output = BasicConstructor.subst(iop)
 225         decode_block = BasicDecode.subst(iop)
 226         exec_output = ThreadRegisterExecute.subst(iop)
 227 }};