5e6918b5721b1b5d7823fe729a85b76867cb22c5
[gem5.git] / src / arch / mips / isa / formats / util.isa
1 // -*- mode:c++ -*-
2
3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
4 // Copyright (c) 2007 MIPS Technologies, Inc.
5 // All rights reserved.
6 //
7 // Redistribution and use in source and binary forms, with or without
8 // modification, are permitted provided that the following conditions are
9 // met: redistributions of source code must retain the above copyright
10 // notice, this list of conditions and the following disclaimer;
11 // redistributions in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution;
14 // neither the name of the copyright holders nor the names of its
15 // contributors may be used to endorse or promote products derived from
16 // this software without specific prior written permission.
17 //
18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29
30 let {{
31 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
32 postacc_code = '', base_class = 'Memory',
33 decode_template = BasicDecode, exec_template_base = ''):
34 # Make sure flags are in lists (convert to lists if not).
35 mem_flags = makeList(mem_flags)
36 inst_flags = makeList(inst_flags)
37
38 # Some CPU models execute the memory operation as an atomic unit,
39 # while others want to separate them into an effective address
40 # computation and a memory access operation. As a result, we need
41 # to generate three StaticInst objects. Note that the latter two
42 # are nested inside the larger "atomic" one.
43
44 # Generate InstObjParams for each of the three objects. Note that
45 # they differ only in the set of code objects contained (which in
46 # turn affects the object's overall operand list).
47 iop = InstObjParams(name, Name, base_class,
48 { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
49 inst_flags)
50
51 if mem_flags:
52 mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
53 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
54 iop.constructor += s
55
56 # select templates
57
58 # The InitiateAcc template is the same for StoreCond templates as the
59 # corresponding Store template..
60 StoreCondInitiateAcc = StoreInitiateAcc
61
62 fullExecTemplate = eval(exec_template_base + 'Execute')
63 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
64 completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
65
66 # (header_output, decoder_output, decode_block, exec_output)
67 return (LoadStoreDeclare.subst(iop),
68 LoadStoreConstructor.subst(iop),
69 decode_template.subst(iop),
70 fullExecTemplate.subst(iop)
71 + initiateAccTemplate.subst(iop)
72 + completeAccTemplate.subst(iop))
73 }};
74
75 output header {{
76 std::string inst2string(MachInst machInst);
77 }};
78
79 output decoder {{
80
81 std::string inst2string(MachInst machInst)
82 {
83 string str = "";
84 uint32_t mask = 0x80000000;
85
86 for(int i=0; i < 32; i++) {
87 if ((machInst & mask) == 0) {
88 str += "0";
89 } else {
90 str += "1";
91 }
92
93 mask = mask >> 1;
94 }
95
96 return str;
97 }
98
99 }};