src/arch/mips/isa/formats/util.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2006 The Regents of The University of Michigan
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 //
  29 // Authors: Steve Reinhardt
  30 //          Korey Sewell
  31
  32 let {{
  33 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
  34                   postacc_code = '', base_class = 'Memory',
  35                   decode_template = BasicDecode, exec_template_base = ''):
  36     # Make sure flags are in lists (convert to lists if not).
  37     mem_flags = makeList(mem_flags)
  38     inst_flags = makeList(inst_flags)
  39
  40     # add hook to get effective addresses into execution trace output.
  41     ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
  42
  43     # Some CPU models execute the memory operation as an atomic unit,
  44     # while others want to separate them into an effective address
  45     # computation and a memory access operation.  As a result, we need
  46     # to generate three StaticInst objects.  Note that the latter two
  47     # are nested inside the larger "atomic" one.
  48
  49     # Generate InstObjParams for each of the three objects.  Note that
  50     # they differ only in the set of code objects contained (which in
  51     # turn affects the object's overall operand list).
  52     iop = InstObjParams(name, Name, base_class,
  53                         { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
  54                         inst_flags)
  55     ea_iop = InstObjParams(name, Name, base_class,
  56                         { 'ea_code':ea_code },
  57                         inst_flags)
  58     memacc_iop = InstObjParams(name, Name, base_class,
  59                         { 'memacc_code':memacc_code, 'postacc_code':postacc_code },
  60                         inst_flags)
  61
  62     if mem_flags:
  63         s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
  64         iop.constructor += s
  65         memacc_iop.constructor += s
  66
  67     # select templates
  68
  69     # The InitiateAcc template is the same for StoreCond templates as the
  70     # corresponding Store template..
  71     StoreCondInitiateAcc = StoreInitiateAcc
  72
  73     memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
  74     fullExecTemplate = eval(exec_template_base + 'Execute')
  75     initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
  76     completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
  77
  78     # (header_output, decoder_output, decode_block, exec_output)
  79     return (LoadStoreDeclare.subst(iop),
  80             EACompConstructor.subst(ea_iop)
  81             + MemAccConstructor.subst(memacc_iop)
  82             + LoadStoreConstructor.subst(iop),
  83             decode_template.subst(iop),
  84             EACompExecute.subst(ea_iop)
  85             + memAccExecTemplate.subst(memacc_iop)
  86             + fullExecTemplate.subst(iop)
  87             + initiateAccTemplate.subst(iop)
  88             + completeAccTemplate.subst(iop))
  89 }};
  90
  91
  92 output header {{
  93         std::string inst2string(MachInst machInst);
  94 }};
  95
  96 output decoder {{
  97
  98 std::string inst2string(MachInst machInst)
  99 {
 100     std::string str = "";
 101     uint32_t mask = 0x80000000;
 102
 103     for(int i=0; i < 32; i++) {
 104         if ((machInst & mask) == 0) {
 105             str += "0";
 106         } else {
 107             str += "1";
 108         }
 109
 110         mask = mask >> 1;
 111     }
 112
 113     return str;
 114 }
 115
 116 }};
 117 output exec {{
 118
 119     using namespace MipsISA;
 120
 121     /// CLEAR ALL CPU INST/EXE HAZARDS
 122     inline void
 123     clear_exe_inst_hazards()
 124     {
 125         //CODE HERE
 126     }
 127
 128
 129     /// Check "FP enabled" machine status bit.  Called when executing any FP
 130     /// instruction in full-system mode.
 131     /// @retval Full-system mode: NoFault if FP is enabled, FenFault
 132     /// if not.  Non-full-system mode: always returns NoFault.
 133 #if FULL_SYSTEM
 134     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
 135     {
 136         Fault fault = NoFault;  // dummy... this ipr access should not fault
 137         if (!Mips34k::ICSR_FPE(xc->readIpr(MipsISA::IPR_ICSR, fault))) {
 138             fault = FloatEnableFault;
 139         }
 140         return fault;
 141     }
 142 #else
 143     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
 144     {
 145         return NoFault;
 146     }
 147 #endif
 148
 149
 150
 151 }};
 152
 153