a79f20572093ab11a34218d398959ab08af7accb
[gem5.git] / src / arch / mips / isa / formats / util.isa
1 // -*- mode:c++ -*-
2
3 // Copyright (c) 2003-2005 The Regents of The University of Michigan
4 // Copyright (c) 2007 MIPS Technologies, Inc.
5 // All rights reserved.
6 //
7 // Redistribution and use in source and binary forms, with or without
8 // modification, are permitted provided that the following conditions are
9 // met: redistributions of source code must retain the above copyright
10 // notice, this list of conditions and the following disclaimer;
11 // redistributions in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution;
14 // neither the name of the copyright holders nor the names of its
15 // contributors may be used to endorse or promote products derived from
16 // this software without specific prior written permission.
17 //
18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 //
30 // Authors: Steve Reinhardt
31 // Korey Sewell
32
33 let {{
34 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
35 postacc_code = '', base_class = 'Memory',
36 decode_template = BasicDecode, exec_template_base = ''):
37 # Make sure flags are in lists (convert to lists if not).
38 mem_flags = makeList(mem_flags)
39 inst_flags = makeList(inst_flags)
40
41 # Some CPU models execute the memory operation as an atomic unit,
42 # while others want to separate them into an effective address
43 # computation and a memory access operation. As a result, we need
44 # to generate three StaticInst objects. Note that the latter two
45 # are nested inside the larger "atomic" one.
46
47 # Generate InstObjParams for each of the three objects. Note that
48 # they differ only in the set of code objects contained (which in
49 # turn affects the object's overall operand list).
50 iop = InstObjParams(name, Name, base_class,
51 { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
52 inst_flags)
53
54 if mem_flags:
55 mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
56 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
57 iop.constructor += s
58
59 # select templates
60
61 # The InitiateAcc template is the same for StoreCond templates as the
62 # corresponding Store template..
63 StoreCondInitiateAcc = StoreInitiateAcc
64
65 fullExecTemplate = eval(exec_template_base + 'Execute')
66 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
67 completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
68
69 # (header_output, decoder_output, decode_block, exec_output)
70 return (LoadStoreDeclare.subst(iop),
71 LoadStoreConstructor.subst(iop),
72 decode_template.subst(iop),
73 fullExecTemplate.subst(iop)
74 + initiateAccTemplate.subst(iop)
75 + completeAccTemplate.subst(iop))
76 }};
77
78 output header {{
79 std::string inst2string(MachInst machInst);
80 }};
81
82 output decoder {{
83
84 std::string inst2string(MachInst machInst)
85 {
86 string str = "";
87 uint32_t mask = 0x80000000;
88
89 for(int i=0; i < 32; i++) {
90 if ((machInst & mask) == 0) {
91 str += "0";
92 } else {
93 str += "1";
94 }
95
96 mask = mask >> 1;
97 }
98
99 return str;
100 }
101
102 }};