src/arch/mips/isa/operands.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2007 MIPS Technologies, Inc.
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
   8 // met: redistributions of source code must retain the above copyright
   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28
  29 def operand_types {{
  30     'sb' : 'int8_t',
  31     'ub' : 'uint8_t',
  32     'sh' : 'int16_t',
  33     'uh' : 'uint16_t',
  34     'sw' : 'int32_t',
  35     'uw' : 'uint32_t',
  36     'sd' : 'int64_t',
  37     'ud' : 'uint64_t',
  38     'sf' : 'float',
  39     'df' : 'double'
  40 }};
  41
  42 def operands {{
  43     #General Purpose Integer Reg Operands
  44     'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
  45     'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
  46     'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
  47
  48     #Immediate Value operand
  49     'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
  50
  51     #Operands used for Link Insts
  52     'R31': ('IntReg', 'uw','31','IsInteger', 4),
  53
  54     #Special Integer Reg operands
  55     'LO0':  ('IntReg', 'uw','INTREG_LO', 'IsInteger', 6),
  56     'HI0':  ('IntReg', 'uw','INTREG_HI', 'IsInteger', 7),
  57
  58     #Bitfield-dependent HI/LO Register Access
  59     'LO_RD_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACDST*3', None, 6),
  60     'HI_RD_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACDST*3', None, 7),
  61     'LO_RS_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACSRC*3', None, 6),
  62     'HI_RS_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACSRC*3', None, 7),
  63
  64     #DSP Special Purpose Integer Operands
  65     'DSPControl': ('IntReg', 'uw', 'INTREG_DSP_CONTROL', None, 8),
  66     'DSPLo0': ('IntReg', 'uw', 'INTREG_LO', None, 1),
  67     'DSPHi0': ('IntReg', 'uw', 'INTREG_HI', None, 1),
  68     'DSPACX0': ('IntReg', 'uw', 'INTREG_DSP_ACX0', None, 1),
  69     'DSPLo1': ('IntReg', 'uw', 'INTREG_DSP_LO1', None, 1),
  70     'DSPHi1': ('IntReg', 'uw', 'INTREG_DSP_HI1', None, 1),
  71     'DSPACX1': ('IntReg', 'uw', 'INTREG_DSP_ACX1', None, 1),
  72     'DSPLo2': ('IntReg', 'uw', 'INTREG_DSP_LO2', None, 1),
  73     'DSPHi2': ('IntReg', 'uw', 'INTREG_DSP_HI2', None, 1),
  74     'DSPACX2': ('IntReg', 'uw', 'INTREG_DSP_ACX2', None, 1),
  75     'DSPLo3': ('IntReg', 'uw', 'INTREG_DSP_LO3', None, 1),
  76     'DSPHi3': ('IntReg', 'uw', 'INTREG_DSP_HI3', None, 1),
  77     'DSPACX3': ('IntReg', 'uw', 'INTREG_DSP_ACX3', None, 1),
  78
  79     #Floating Point Reg Operands
  80     'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
  81     'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
  82     'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
  83     'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
  84
  85     #Special Purpose Floating Point Control Reg Operands
  86     'FIR':  ('FloatReg', 'uw', 'FLOATREG_FIR', 'IsFloating', 1),
  87     'FCCR': ('FloatReg', 'uw', 'FLOATREG_FCCR', 'IsFloating', 2),
  88     'FEXR': ('FloatReg', 'uw', 'FLOATREG_FEXR', 'IsFloating', 3),
  89     'FENR': ('FloatReg', 'uw', 'FLOATREG_FENR', 'IsFloating', 3),
  90     'FCSR': ('FloatReg', 'uw', 'FLOATREG_FCSR', 'IsFloating', 3),
  91
  92     #Operands For Paired Singles FP Operations
  93     'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
  94     'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
  95     'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
  96     'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
  97     'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
  98     'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
  99     'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
 100     'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
 101
 102     #Status Control Reg
 103     'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1),
 104
 105     #LL Flag
 106     'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
 107
 108     #Thread pointer value for SE mode
 109     'TpValue': ('ControlReg', 'ud', 'MISCREG_TP_VALUE', None, 1),
 110
 111     # Index Register
 112     'Index': ('ControlReg','uw','MISCREG_INDEX',None,1),
 113
 114
 115     'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
 116
 117     #MT Control Regs
 118     'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1),
 119     'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1),
 120     'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1),
 121     'TCStatus': ('ControlReg', 'uw', 'MISCREG_TC_STATUS', None, 1),
 122     'TCRestart': ('ControlReg', 'uw', 'MISCREG_TC_RESTART', None, 1),
 123     'VPEConf0': ('ControlReg', 'uw', 'MISCREG_VPE_CONF0', None, 1),
 124     'VPEControl': ('ControlReg', 'uw', 'MISCREG_VPE_CONTROL', None, 1),
 125     'YQMask': ('ControlReg', 'uw', 'MISCREG_YQMASK', None, 1),
 126
 127     #CP0 Control Regs
 128     'EntryHi': ('ControlReg','uw', 'MISCREG_ENTRYHI',None,1),
 129     'EntryLo0': ('ControlReg','uw', 'MISCREG_ENTRYLO0',None,1),
 130     'EntryLo1': ('ControlReg','uw', 'MISCREG_ENTRYLO1',None,1),
 131     'PageMask': ('ControlReg','uw', 'MISCREG_PAGEMASK',None,1),
 132     'Random': ('ControlReg','uw', 'MISCREG_CP0_RANDOM',None,1),
 133     'ErrorEPC': ('ControlReg','uw', 'MISCREG_ERROR_EPC',None,1),
 134     'EPC': ('ControlReg','uw', 'MISCREG_EPC',None,1),
 135     'DEPC': ('ControlReg','uw', 'MISCREG_DEPC',None,1),
 136     'IntCtl': ('ControlReg','uw', 'MISCREG_INTCTL',None,1),
 137     'SRSCtl': ('ControlReg','uw', 'MISCREG_SRSCTL',None,1),
 138     'Config': ('ControlReg','uw', 'MISCREG_CONFIG',None,1),
 139     'Config3': ('ControlReg','uw', 'MISCREG_CONFIG3',None,1),
 140     'Config1': ('ControlReg','uw', 'MISCREG_CONFIG1',None,1),
 141     'Config2': ('ControlReg','uw', 'MISCREG_CONFIG2',None,1),
 142     'PageGrain': ('ControlReg','uw', 'MISCREG_PAGEGRAIN',None,1),
 143     'Debug': ('ControlReg','uw', 'MISCREG_DEBUG',None,1),
 144     'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1),
 145
 146     #Memory Operand
 147     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 148
 149     #Program Counter Operands
 150     'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 4),
 151     'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 4),
 152     'NNPC': ('PCState', 'uw', 'nnpc', (None, None, 'IsControl'), 4)
 153 }};