2 * Copyright (c) 2009 The Regents of The University of Michigan
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6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
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31 #include "arch/mips/isa.hh"
32 #include "arch/mips/mt.hh"
33 #include "arch/mips/mt_constants.hh"
34 #include "arch/mips/pra_constants.hh"
35 #include "base/bitfield.hh"
36 #include "cpu/base.hh"
37 #include "cpu/thread_context.hh"
38 #include "debug/MipsPRA.hh"
39 #include "params/MipsISA.hh"
45 ISA::miscRegNames
[NumMiscRegs
] =
47 "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
48 "Random", "VPEControl", "VPEConf0", "VPEConf1",
49 "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
50 "EntryLo0", "TCStatus", "TCBind", "TCRestart",
51 "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
52 "EntryLo1", "", "", "", "", "", "", "",
53 "Context", "ContextConfig", "", "", "", "", "", "",
54 "PageMask", "PageGrain", "", "", "", "", "", "",
55 "Wired", "SRSConf0", "SRCConf1", "SRSConf2",
56 "SRSConf3", "SRSConf4", "", "",
57 "HWREna", "", "", "", "", "", "", "",
58 "BadVAddr", "", "", "", "", "", "", "",
59 "Count", "", "", "", "", "", "", "",
60 "EntryHi", "", "", "", "", "", "", "",
61 "Compare", "", "", "", "", "", "", "",
62 "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
63 "Cause", "", "", "", "", "", "", "",
64 "EPC", "", "", "", "", "", "", "",
65 "PRId", "EBase", "", "", "", "", "", "",
66 "Config", "Config1", "Config2", "Config3", "", "", "", "",
67 "LLAddr", "", "", "", "", "", "", "",
68 "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
69 "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
70 "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
71 "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
72 "XCContext64", "", "", "", "", "", "", "",
73 "", "", "", "", "", "", "", "",
74 "", "", "", "", "", "", "", "",
75 "Debug", "TraceControl1", "TraceControl2", "UserTraceData",
76 "TraceBPC", "", "", "",
77 "DEPC", "", "", "", "", "", "", "",
78 "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
79 "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
80 "ErrCtl", "", "", "", "", "", "", "",
81 "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
82 "TagLo0", "DataLo1", "TagLo2", "DataLo3",
83 "TagLo4", "DataLo5", "TagLo6", "DataLo7",
84 "TagHi0", "DataHi1", "TagHi2", "DataHi3",
85 "TagHi4", "DataHi5", "TagHi6", "DataHi7",
86 "ErrorEPC", "", "", "", "", "", "", "",
87 "DESAVE", "", "", "", "", "", "", "",
93 numThreads(p
->num_threads
), numVpes(p
->num_vpes
)
95 miscRegFile
.resize(NumMiscRegs
);
96 bankType
.resize(NumMiscRegs
);
98 for (int i
=0; i
< NumMiscRegs
; i
++) {
99 miscRegFile
[i
].resize(1);
100 bankType
[i
] = perProcessor
;
103 miscRegFile_WriteMask
.resize(NumMiscRegs
);
105 for (int i
= 0; i
< NumMiscRegs
; i
++) {
106 miscRegFile_WriteMask
[i
].push_back(0);
109 // Initialize all Per-VPE regs
110 uint32_t per_vpe_regs
[] = { MISCREG_VPE_CONTROL
,
111 MISCREG_VPE_CONF0
, MISCREG_VPE_CONF1
,
113 MISCREG_VPE_SCHEDULE
, MISCREG_VPE_SCHEFBACK
,
114 MISCREG_VPE_OPT
, MISCREG_SRS_CONF0
,
115 MISCREG_SRS_CONF1
, MISCREG_SRS_CONF2
,
116 MISCREG_SRS_CONF3
, MISCREG_SRS_CONF4
,
119 uint32_t num_vpe_regs
= sizeof(per_vpe_regs
) / 4;
120 for (int i
= 0; i
< num_vpe_regs
; i
++) {
122 miscRegFile
[per_vpe_regs
[i
]].resize(numVpes
);
124 bankType
[per_vpe_regs
[i
]] = perVirtProcessor
;
127 // Initialize all Per-TC regs
128 uint32_t per_tc_regs
[] = { MISCREG_STATUS
,
129 MISCREG_TC_STATUS
, MISCREG_TC_BIND
,
130 MISCREG_TC_RESTART
, MISCREG_TC_HALT
,
131 MISCREG_TC_CONTEXT
, MISCREG_TC_SCHEDULE
,
132 MISCREG_TC_SCHEFBACK
,
133 MISCREG_DEBUG
, MISCREG_LLADDR
135 uint32_t num_tc_regs
= sizeof(per_tc_regs
) / 4;
137 for (int i
= 0; i
< num_tc_regs
; i
++) {
138 miscRegFile
[per_tc_regs
[i
]].resize(numThreads
);
139 bankType
[per_tc_regs
[i
]] = perThreadContext
;
145 const MipsISAParams
*
148 return dynamic_cast<const Params
*>(_params
);
154 for(int i
= 0; i
< NumMiscRegs
; i
++) {
155 for (int j
= 0; j
< miscRegFile
[i
].size(); j
++)
156 miscRegFile
[i
][j
] = 0;
158 for (int k
= 0; k
< miscRegFile_WriteMask
[i
].size(); k
++)
159 miscRegFile_WriteMask
[i
][k
] = (long unsigned int)(-1);
167 DPRINTF(MipsPRA
, "Resetting CP0 State with %i TCs and %i VPEs\n",
168 numThreads
, numVpes
);
171 panic("CP state must be set before the following code is used");
173 // Do Default CP0 initialization HERE
175 // Do Initialization for MT cores here (eventually use
176 // core_name parameter to toggle this initialization)
177 // ===================================================
178 DPRINTF(MipsPRA
, "Initializing CP0 State.... ");
180 PRIdReg procId
= readMiscRegNoEffect(MISCREG_PRID
);
181 procId
.coOp
= cp
.CP0_PRId_CompanyOptions
;
182 procId
.coId
= cp
.CP0_PRId_CompanyID
;
183 procId
.procId
= cp
.CP0_PRId_ProcessorID
;
184 procId
.rev
= cp
.CP0_PRId_Revision
;
185 setMiscRegNoEffect(MISCREG_PRID
, procId
);
187 // Now, create Write Mask for ProcID register
188 MiscReg procIDMask
= 0; // Read-Only register
189 replaceBits(procIDMask
, 0, 32, 0);
190 setRegMask(MISCREG_PRID
, procIDMask
);
193 ConfigReg cfg
= readMiscRegNoEffect(MISCREG_CONFIG
);
194 cfg
.be
= cp
.CP0_Config_BE
;
195 cfg
.at
= cp
.CP0_Config_AT
;
196 cfg
.ar
= cp
.CP0_Config_AR
;
197 cfg
.mt
= cp
.CP0_Config_MT
;
198 cfg
.vi
= cp
.CP0_Config_VI
;
200 setMiscRegNoEffect(MISCREG_CONFIG
, cfg
);
201 // Now, create Write Mask for Config register
202 MiscReg cfg_Mask
= 0x7FFF0007;
203 replaceBits(cfg_Mask
, 0, 32, 0);
204 setRegMask(MISCREG_CONFIG
, cfg_Mask
);
207 Config1Reg cfg1
= readMiscRegNoEffect(MISCREG_CONFIG1
);
208 cfg1
.mmuSize
= cp
.CP0_Config1_MMU
;
209 cfg1
.is
= cp
.CP0_Config1_IS
;
210 cfg1
.il
= cp
.CP0_Config1_IL
;
211 cfg1
.ia
= cp
.CP0_Config1_IA
;
212 cfg1
.ds
= cp
.CP0_Config1_DS
;
213 cfg1
.dl
= cp
.CP0_Config1_DL
;
214 cfg1
.da
= cp
.CP0_Config1_DA
;
215 cfg1
.fp
= cp
.CP0_Config1_FP
;
216 cfg1
.ep
= cp
.CP0_Config1_EP
;
217 cfg1
.wr
= cp
.CP0_Config1_WR
;
218 cfg1
.md
= cp
.CP0_Config1_MD
;
219 cfg1
.c2
= cp
.CP0_Config1_C2
;
220 cfg1
.pc
= cp
.CP0_Config1_PC
;
221 cfg1
.m
= cp
.CP0_Config1_M
;
222 setMiscRegNoEffect(MISCREG_CONFIG1
, cfg1
);
223 // Now, create Write Mask for Config register
224 MiscReg cfg1_Mask
= 0; // Read Only Register
225 replaceBits(cfg1_Mask
, 0, 32, 0);
226 setRegMask(MISCREG_CONFIG1
, cfg1_Mask
);
229 Config2Reg cfg2
= readMiscRegNoEffect(MISCREG_CONFIG2
);
230 cfg2
.tu
= cp
.CP0_Config2_TU
;
231 cfg2
.ts
= cp
.CP0_Config2_TS
;
232 cfg2
.tl
= cp
.CP0_Config2_TL
;
233 cfg2
.ta
= cp
.CP0_Config2_TA
;
234 cfg2
.su
= cp
.CP0_Config2_SU
;
235 cfg2
.ss
= cp
.CP0_Config2_SS
;
236 cfg2
.sl
= cp
.CP0_Config2_SL
;
237 cfg2
.sa
= cp
.CP0_Config2_SA
;
238 cfg2
.m
= cp
.CP0_Config2_M
;
239 setMiscRegNoEffect(MISCREG_CONFIG2
, cfg2
);
240 // Now, create Write Mask for Config register
241 MiscReg cfg2_Mask
= 0x7000F000; // Read Only Register
242 replaceBits(cfg2_Mask
, 0, 32, 0);
243 setRegMask(MISCREG_CONFIG2
, cfg2_Mask
);
246 Config3Reg cfg3
= readMiscRegNoEffect(MISCREG_CONFIG3
);
247 cfg3
.dspp
= cp
.CP0_Config3_DSPP
;
248 cfg3
.lpa
= cp
.CP0_Config3_LPA
;
249 cfg3
.veic
= cp
.CP0_Config3_VEIC
;
250 cfg3
.vint
= cp
.CP0_Config3_VInt
;
251 cfg3
.sp
= cp
.CP0_Config3_SP
;
252 cfg3
.mt
= cp
.CP0_Config3_MT
;
253 cfg3
.sm
= cp
.CP0_Config3_SM
;
254 cfg3
.tl
= cp
.CP0_Config3_TL
;
255 setMiscRegNoEffect(MISCREG_CONFIG3
, cfg3
);
256 // Now, create Write Mask for Config register
257 MiscReg cfg3_Mask
= 0; // Read Only Register
258 replaceBits(cfg3_Mask
, 0, 32, 0);
259 setRegMask(MISCREG_CONFIG3
, cfg3_Mask
);
262 EBaseReg eBase
= readMiscRegNoEffect(MISCREG_EBASE
);
263 eBase
.cpuNum
= cp
.CP0_EBase_CPUNum
;
264 replaceBits(eBase
, 31, 31, 1);
265 setMiscRegNoEffect(MISCREG_EBASE
, eBase
);
266 // Now, create Write Mask for Config register
267 MiscReg EB_Mask
= 0x3FFFF000;// Except Exception Base, the
268 // entire register is read only
269 replaceBits(EB_Mask
, 0, 32, 0);
270 setRegMask(MISCREG_EBASE
, EB_Mask
);
272 // SRS Control - HSS (Highest Shadow Set)
273 SRSCtlReg scsCtl
= readMiscRegNoEffect(MISCREG_SRSCTL
);
274 scsCtl
.hss
= cp
.CP0_SrsCtl_HSS
;
275 setMiscRegNoEffect(MISCREG_SRSCTL
, scsCtl
);
276 // Now, create Write Mask for the SRS Ctl register
277 MiscReg SC_Mask
= 0x0000F3C0;
278 replaceBits(SC_Mask
, 0, 32, 0);
279 setRegMask(MISCREG_SRSCTL
, SC_Mask
);
281 // IntCtl - IPTI, IPPCI
282 IntCtlReg intCtl
= readMiscRegNoEffect(MISCREG_INTCTL
);
283 intCtl
.ipti
= cp
.CP0_IntCtl_IPTI
;
284 intCtl
.ippci
= cp
.CP0_IntCtl_IPPCI
;
285 setMiscRegNoEffect(MISCREG_INTCTL
, intCtl
);
286 // Now, create Write Mask for the IntCtl register
287 MiscReg IC_Mask
= 0x000003E0;
288 replaceBits(IC_Mask
, 0, 32, 0);
289 setRegMask(MISCREG_INTCTL
, IC_Mask
);
291 // Watch Hi - M - FIXME (More than 1 Watch register)
292 WatchHiReg watchHi
= readMiscRegNoEffect(MISCREG_WATCHHI0
);
293 watchHi
.m
= cp
.CP0_WatchHi_M
;
294 setMiscRegNoEffect(MISCREG_WATCHHI0
, watchHi
);
295 // Now, create Write Mask for the IntCtl register
296 MiscReg wh_Mask
= 0x7FFF0FFF;
297 replaceBits(wh_Mask
, 0, 32, 0);
298 setRegMask(MISCREG_WATCHHI0
, wh_Mask
);
300 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
301 PerfCntCtlReg perfCntCtl
= readMiscRegNoEffect(MISCREG_PERFCNT0
);
302 perfCntCtl
.m
= cp
.CP0_PerfCtr_M
;
303 perfCntCtl
.w
= cp
.CP0_PerfCtr_W
;
304 setMiscRegNoEffect(MISCREG_PERFCNT0
, perfCntCtl
);
305 // Now, create Write Mask for the IntCtl register
306 MiscReg pc_Mask
= 0x00007FF;
307 replaceBits(pc_Mask
, 0, 32, 0);
308 setRegMask(MISCREG_PERFCNT0
, pc_Mask
);
311 setMiscRegNoEffect(MISCREG_CP0_RANDOM
, 63);
312 // Now, create Write Mask for the IntCtl register
313 MiscReg random_Mask
= 0;
314 replaceBits(random_Mask
, 0, 32, 0);
315 setRegMask(MISCREG_CP0_RANDOM
, random_Mask
);
318 PageGrainReg pageGrain
= readMiscRegNoEffect(MISCREG_PAGEGRAIN
);
319 pageGrain
.esp
= cp
.CP0_Config3_SP
;
320 setMiscRegNoEffect(MISCREG_PAGEGRAIN
, pageGrain
);
321 // Now, create Write Mask for the IntCtl register
322 MiscReg pg_Mask
= 0x10000000;
323 replaceBits(pg_Mask
, 0, 32, 0);
324 setRegMask(MISCREG_PAGEGRAIN
, pg_Mask
);
327 StatusReg status
= readMiscRegNoEffect(MISCREG_STATUS
);
328 // Only CU0 and IE are modified on a reset - everything else needs
329 // to be controlled on a per CPU model basis
331 // Enable CP0 on reset
334 // Enable ERL bit on a reset
336 // Enable BEV bit on a reset
339 setMiscRegNoEffect(MISCREG_STATUS
, status
);
340 // Now, create Write Mask for the Status register
341 MiscReg stat_Mask
= 0xFF78FF17;
342 replaceBits(stat_Mask
, 0, 32, 0);
343 setRegMask(MISCREG_STATUS
, stat_Mask
);
347 MVPConf0Reg mvpConf0
= readMiscRegNoEffect(MISCREG_MVP_CONF0
);
349 mvpConf0
.pvpe
= numVpes
- 1;
350 mvpConf0
.ptc
= numThreads
- 1;
351 setMiscRegNoEffect(MISCREG_MVP_CONF0
, mvpConf0
);
354 VPEConf0Reg vpeConf0
= readMiscRegNoEffect(MISCREG_VPE_CONF0
);
356 setMiscRegNoEffect(MISCREG_VPE_CONF0
, vpeConf0
);
359 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
360 TCBindReg tcBind
= readMiscRegNoEffect(MISCREG_TC_BIND
, tid
);
362 setMiscRegNoEffect(MISCREG_TC_BIND
, tcBind
, tid
);
365 TCHaltReg tcHalt
= readMiscRegNoEffect(MISCREG_TC_HALT
);
367 setMiscRegNoEffect(MISCREG_TC_HALT
, tcHalt
);
370 // Set TCStatus Activated to 1 for the initial thread that is running
371 TCStatusReg tcStatus
= readMiscRegNoEffect(MISCREG_TC_STATUS
);
373 setMiscRegNoEffect(MISCREG_TC_STATUS
, tcStatus
);
375 // Set Dynamically Allocatable bit to 1 for all other threads
376 for (ThreadID tid
= 1; tid
< numThreads
; tid
++) {
377 tcStatus
= readMiscRegNoEffect(MISCREG_TC_STATUS
, tid
);
379 setMiscRegNoEffect(MISCREG_TC_STATUS
, tcStatus
, tid
);
383 MiscReg mask
= 0x7FFFFFFF;
385 // Now, create Write Mask for the Index register
386 replaceBits(mask
, 0, 32, 0);
387 setRegMask(MISCREG_INDEX
, mask
);
390 replaceBits(mask
, 0, 32, 0);
391 setRegMask(MISCREG_ENTRYLO0
, mask
);
392 setRegMask(MISCREG_ENTRYLO1
, mask
);
395 replaceBits(mask
, 0, 32, 0);
396 setRegMask(MISCREG_CONTEXT
, mask
);
399 replaceBits(mask
, 0, 32, 0);
400 setRegMask(MISCREG_PAGEMASK
, mask
);
403 replaceBits(mask
, 0, 32, 0);
404 setRegMask(MISCREG_BADVADDR
, mask
);
405 setRegMask(MISCREG_LLADDR
, mask
);
408 replaceBits(mask
, 0, 32, 0);
409 setRegMask(MISCREG_CAUSE
, mask
);
414 ISA::getVPENum(ThreadID tid
)
416 TCBindReg tcBind
= miscRegFile
[MISCREG_TC_BIND
][tid
];
417 return tcBind
.curVPE
;
421 ISA::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
423 unsigned reg_sel
= (bankType
[misc_reg
] == perThreadContext
)
424 ? tid
: getVPENum(tid
);
425 DPRINTF(MipsPRA
, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
426 misc_reg
/ 8, misc_reg
% 8, miscRegNames
[misc_reg
],
427 miscRegFile
[misc_reg
][reg_sel
]);
428 return miscRegFile
[misc_reg
][reg_sel
];
431 //@TODO: MIPS MT's register view automatically connects
432 // Status to TCStatus depending on current thread
433 //template <class TC>
435 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
, ThreadID tid
)
437 unsigned reg_sel
= (bankType
[misc_reg
] == perThreadContext
)
438 ? tid
: getVPENum(tid
);
440 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
441 misc_reg
/ 8, misc_reg
% 8, miscRegNames
[misc_reg
],
442 miscRegFile
[misc_reg
][reg_sel
]);
444 return miscRegFile
[misc_reg
][reg_sel
];
448 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
450 unsigned reg_sel
= (bankType
[misc_reg
] == perThreadContext
)
451 ? tid
: getVPENum(tid
);
453 "[tid:%i]: Setting (direct set) CP0 Register:%u "
454 "Select:%u (%s) to %#x.\n",
455 tid
, misc_reg
/ 8, misc_reg
% 8, miscRegNames
[misc_reg
], val
);
457 miscRegFile
[misc_reg
][reg_sel
] = val
;
461 ISA::setRegMask(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
463 unsigned reg_sel
= (bankType
[misc_reg
] == perThreadContext
)
464 ? tid
: getVPENum(tid
);
466 "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
467 tid
, misc_reg
/ 8, misc_reg
% 8, miscRegNames
[misc_reg
], val
);
468 miscRegFile_WriteMask
[misc_reg
][reg_sel
] = val
;
471 // PROGRAMMER'S NOTES:
472 // (1) Some CP0 Registers have fields that cannot
473 // be overwritten. Make sure to handle those particular registers
476 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
,
477 ThreadContext
*tc
, ThreadID tid
)
479 int reg_sel
= (bankType
[misc_reg
] == perThreadContext
)
480 ? tid
: getVPENum(tid
);
483 "[tid:%i]: Setting CP0 Register:%u "
484 "Select:%u (%s) to %#x, with effect.\n",
485 tid
, misc_reg
/ 8, misc_reg
% 8, miscRegNames
[misc_reg
], val
);
487 MiscReg cp0_val
= filterCP0Write(misc_reg
, reg_sel
, val
);
489 miscRegFile
[misc_reg
][reg_sel
] = cp0_val
;
491 scheduleCP0Update(tc
->getCpuPtr(), Cycles(1));
495 * This method doesn't need to adjust the Control Register Offset
496 * since it has already been done in the calling method
500 ISA::filterCP0Write(int misc_reg
, int reg_sel
, const MiscReg
&val
)
502 MiscReg retVal
= val
;
504 // Mask off read-only regions
505 retVal
&= miscRegFile_WriteMask
[misc_reg
][reg_sel
];
506 MiscReg curVal
= miscRegFile
[misc_reg
][reg_sel
];
507 // Mask off current alue with inverse mask (clear writeable bits)
508 curVal
&= (~miscRegFile_WriteMask
[misc_reg
][reg_sel
]);
509 retVal
|= curVal
; // Combine the two
511 "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
512 "current val: %lx, written val: %x\n",
513 miscRegFile_WriteMask
[misc_reg
][reg_sel
],
514 ~miscRegFile_WriteMask
[misc_reg
][reg_sel
],
515 val
, miscRegFile
[misc_reg
][reg_sel
], retVal
);
520 ISA::scheduleCP0Update(BaseCPU
*cpu
, Cycles delay
)
526 CP0Event
*cp0_event
= new CP0Event(this, cpu
, UpdateCP0
);
527 cpu
->schedule(cp0_event
, cpu
->clockEdge(delay
));
532 ISA::updateCPU(BaseCPU
*cpu
)
534 ///////////////////////////////////////////////////////////////////
536 // EVALUATE CP0 STATE FOR MIPS MT
538 ///////////////////////////////////////////////////////////////////
539 MVPConf0Reg mvpConf0
= readMiscRegNoEffect(MISCREG_MVP_CONF0
);
540 ThreadID num_threads
= mvpConf0
.ptc
+ 1;
542 for (ThreadID tid
= 0; tid
< num_threads
; tid
++) {
543 TCStatusReg tcStatus
= readMiscRegNoEffect(MISCREG_TC_STATUS
, tid
);
544 TCHaltReg tcHalt
= readMiscRegNoEffect(MISCREG_TC_HALT
, tid
);
546 //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
547 if (tcHalt
.h
== 1 || tcStatus
.a
== 0) {
548 haltThread(cpu
->getContext(tid
));
549 } else if (tcHalt
.h
== 0 && tcStatus
.a
== 1) {
550 restoreThread(cpu
->getContext(tid
));
554 num_threads
= mvpConf0
.ptc
+ 1;
556 // Toggle update flag after we finished updating
560 ISA::CP0Event::CP0Event(CP0
*_cp0
, BaseCPU
*_cpu
, CP0EventType e_type
)
561 : Event(CPU_Tick_Pri
), cp0(_cp0
), cpu(_cpu
), cp0EventType(e_type
)
565 ISA::CP0Event::process()
567 switch (cp0EventType
)
576 ISA::CP0Event::description() const
578 return "Coprocessor-0 event";
582 ISA::CP0Event::scheduleEvent(Cycles delay
)
584 cpu
->reschedule(this, cpu
->clockEdge(delay
), true);
588 ISA::CP0Event::unscheduleEvent()
597 MipsISAParams::create()
599 return new MipsISA::ISA(this);