2 * Copyright (c) 2009 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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31 #include "arch/mips/isa.hh"
32 #include "arch/mips/mt.hh"
33 #include "arch/mips/mt_constants.hh"
34 #include "arch/mips/pra_constants.hh"
35 #include "base/bitfield.hh"
36 #include "cpu/base.hh"
37 #include "cpu/thread_context.hh"
43 ISA::miscRegNames
[NumMiscRegs
] =
45 "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
46 "Random", "VPEControl", "VPEConf0", "VPEConf1",
47 "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
48 "EntryLo0", "TCStatus", "TCBind", "TCRestart",
49 "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
50 "EntryLo1", "", "", "", "", "", "", "",
51 "Context", "ContextConfig", "", "", "", "", "", "",
52 "PageMask", "PageGrain", "", "", "", "", "", "",
53 "Wired", "SRSConf0", "SRCConf1", "SRSConf2",
54 "SRSConf3", "SRSConf4", "", "",
55 "HWREna", "", "", "", "", "", "", "",
56 "BadVAddr", "", "", "", "", "", "", "",
57 "Count", "", "", "", "", "", "", "",
58 "EntryHi", "", "", "", "", "", "", "",
59 "Compare", "", "", "", "", "", "", "",
60 "Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
61 "Cause", "", "", "", "", "", "", "",
62 "EPC", "", "", "", "", "", "", "",
63 "PRId", "EBase", "", "", "", "", "", "",
64 "Config", "Config1", "Config2", "Config3", "", "", "", "",
65 "LLAddr", "", "", "", "", "", "", "",
66 "WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
67 "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
68 "WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
69 "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
70 "XCContext64", "", "", "", "", "", "", "",
71 "", "", "", "", "", "", "", "",
72 "", "", "", "", "", "", "", "",
73 "Debug", "TraceControl1", "TraceControl2", "UserTraceData",
74 "TraceBPC", "", "", "",
75 "DEPC", "", "", "", "", "", "", "",
76 "PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
77 "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
78 "ErrCtl", "", "", "", "", "", "", "",
79 "CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
80 "TagLo0", "DataLo1", "TagLo2", "DataLo3",
81 "TagLo4", "DataLo5", "TagLo6", "DataLo7",
82 "TagHi0", "DataHi1", "TagHi2", "DataHi3",
83 "TagHi4", "DataHi5", "TagHi6", "DataHi7",
84 "ErrorEPC", "", "", "", "", "", "", "",
85 "DESAVE", "", "", "", "", "", "", "",
89 ISA::ISA(uint8_t num_threads
, uint8_t num_vpes
)
91 numThreads
= num_threads
;
94 miscRegFile
.resize(NumMiscRegs
);
95 bankType
.resize(NumMiscRegs
);
97 for (int i
=0; i
< NumMiscRegs
; i
++) {
98 miscRegFile
[i
].resize(1);
99 bankType
[i
] = perProcessor
;
102 miscRegFile_WriteMask
.resize(NumMiscRegs
);
104 for (int i
= 0; i
< NumMiscRegs
; i
++) {
105 miscRegFile_WriteMask
[i
].push_back(0);
108 // Initialize all Per-VPE regs
109 uint32_t per_vpe_regs
[] = { MISCREG_VPE_CONTROL
,
110 MISCREG_VPE_CONF0
, MISCREG_VPE_CONF1
,
112 MISCREG_VPE_SCHEDULE
, MISCREG_VPE_SCHEFBACK
,
113 MISCREG_VPE_OPT
, MISCREG_SRS_CONF0
,
114 MISCREG_SRS_CONF1
, MISCREG_SRS_CONF2
,
115 MISCREG_SRS_CONF3
, MISCREG_SRS_CONF4
,
118 uint32_t num_vpe_regs
= sizeof(per_vpe_regs
) / 4;
119 for (int i
= 0; i
< num_vpe_regs
; i
++) {
121 miscRegFile
[per_vpe_regs
[i
]].resize(numVpes
);
123 bankType
[per_vpe_regs
[i
]] = perVirtProcessor
;
126 // Initialize all Per-TC regs
127 uint32_t per_tc_regs
[] = { MISCREG_STATUS
,
128 MISCREG_TC_STATUS
, MISCREG_TC_BIND
,
129 MISCREG_TC_RESTART
, MISCREG_TC_HALT
,
130 MISCREG_TC_CONTEXT
, MISCREG_TC_SCHEDULE
,
131 MISCREG_TC_SCHEFBACK
,
132 MISCREG_DEBUG
, MISCREG_LLADDR
134 uint32_t num_tc_regs
= sizeof(per_tc_regs
) / 4;
136 for (int i
= 0; i
< num_tc_regs
; i
++) {
137 miscRegFile
[per_tc_regs
[i
]].resize(numThreads
);
138 bankType
[per_tc_regs
[i
]] = perThreadContext
;
147 for(int i
= 0; i
< NumMiscRegs
; i
++) {
148 for (int j
= 0; j
< miscRegFile
[i
].size(); j
++)
149 miscRegFile
[i
][j
] = 0;
151 for (int k
= 0; k
< miscRegFile_WriteMask
[i
].size(); k
++)
152 miscRegFile_WriteMask
[i
][k
] = (long unsigned int)(-1);
160 DPRINTF(MipsPRA
, "Resetting CP0 State with %i TCs and %i VPEs\n",
161 numThreads
, numVpes
);
164 panic("CP state must be set before the following code is used");
166 // Do Default CP0 initialization HERE
168 // Do Initialization for MT cores here (eventually use
169 // core_name parameter to toggle this initialization)
170 // ===================================================
171 DPRINTF(MipsPRA
, "Initializing CP0 State.... ");
173 PRIdReg procId
= readMiscRegNoEffect(MISCREG_PRID
);
174 procId
.coOp
= cp
.CP0_PRId_CompanyOptions
;
175 procId
.coId
= cp
.CP0_PRId_CompanyID
;
176 procId
.procId
= cp
.CP0_PRId_ProcessorID
;
177 procId
.rev
= cp
.CP0_PRId_Revision
;
178 setMiscRegNoEffect(MISCREG_PRID
, procId
);
180 // Now, create Write Mask for ProcID register
181 MiscReg procIDMask
= 0; // Read-Only register
182 replaceBits(procIDMask
, 0, 32, 0);
183 setRegMask(MISCREG_PRID
, procIDMask
);
186 ConfigReg cfg
= readMiscRegNoEffect(MISCREG_CONFIG
);
187 cfg
.be
= cp
.CP0_Config_BE
;
188 cfg
.at
= cp
.CP0_Config_AT
;
189 cfg
.ar
= cp
.CP0_Config_AR
;
190 cfg
.mt
= cp
.CP0_Config_MT
;
191 cfg
.vi
= cp
.CP0_Config_VI
;
193 setMiscRegNoEffect(MISCREG_CONFIG
, cfg
);
194 // Now, create Write Mask for Config register
195 MiscReg cfg_Mask
= 0x7FFF0007;
196 replaceBits(cfg_Mask
, 0, 32, 0);
197 setRegMask(MISCREG_CONFIG
, cfg_Mask
);
200 Config1Reg cfg1
= readMiscRegNoEffect(MISCREG_CONFIG1
);
201 cfg1
.mmuSize
= cp
.CP0_Config1_MMU
;
202 cfg1
.is
= cp
.CP0_Config1_IS
;
203 cfg1
.il
= cp
.CP0_Config1_IL
;
204 cfg1
.ia
= cp
.CP0_Config1_IA
;
205 cfg1
.ds
= cp
.CP0_Config1_DS
;
206 cfg1
.dl
= cp
.CP0_Config1_DL
;
207 cfg1
.da
= cp
.CP0_Config1_DA
;
208 cfg1
.fp
= cp
.CP0_Config1_FP
;
209 cfg1
.ep
= cp
.CP0_Config1_EP
;
210 cfg1
.wr
= cp
.CP0_Config1_WR
;
211 cfg1
.md
= cp
.CP0_Config1_MD
;
212 cfg1
.c2
= cp
.CP0_Config1_C2
;
213 cfg1
.pc
= cp
.CP0_Config1_PC
;
214 cfg1
.m
= cp
.CP0_Config1_M
;
215 setMiscRegNoEffect(MISCREG_CONFIG1
, cfg1
);
216 // Now, create Write Mask for Config register
217 MiscReg cfg1_Mask
= 0; // Read Only Register
218 replaceBits(cfg1_Mask
, 0, 32, 0);
219 setRegMask(MISCREG_CONFIG1
, cfg1_Mask
);
222 Config2Reg cfg2
= readMiscRegNoEffect(MISCREG_CONFIG2
);
223 cfg2
.tu
= cp
.CP0_Config2_TU
;
224 cfg2
.ts
= cp
.CP0_Config2_TS
;
225 cfg2
.tl
= cp
.CP0_Config2_TL
;
226 cfg2
.ta
= cp
.CP0_Config2_TA
;
227 cfg2
.su
= cp
.CP0_Config2_SU
;
228 cfg2
.ss
= cp
.CP0_Config2_SS
;
229 cfg2
.sl
= cp
.CP0_Config2_SL
;
230 cfg2
.sa
= cp
.CP0_Config2_SA
;
231 cfg2
.m
= cp
.CP0_Config2_M
;
232 setMiscRegNoEffect(MISCREG_CONFIG2
, cfg2
);
233 // Now, create Write Mask for Config register
234 MiscReg cfg2_Mask
= 0x7000F000; // Read Only Register
235 replaceBits(cfg2_Mask
, 0, 32, 0);
236 setRegMask(MISCREG_CONFIG2
, cfg2_Mask
);
239 Config3Reg cfg3
= readMiscRegNoEffect(MISCREG_CONFIG3
);
240 cfg3
.dspp
= cp
.CP0_Config3_DSPP
;
241 cfg3
.lpa
= cp
.CP0_Config3_LPA
;
242 cfg3
.veic
= cp
.CP0_Config3_VEIC
;
243 cfg3
.vint
= cp
.CP0_Config3_VInt
;
244 cfg3
.sp
= cp
.CP0_Config3_SP
;
245 cfg3
.mt
= cp
.CP0_Config3_MT
;
246 cfg3
.sm
= cp
.CP0_Config3_SM
;
247 cfg3
.tl
= cp
.CP0_Config3_TL
;
248 setMiscRegNoEffect(MISCREG_CONFIG3
, cfg3
);
249 // Now, create Write Mask for Config register
250 MiscReg cfg3_Mask
= 0; // Read Only Register
251 replaceBits(cfg3_Mask
, 0, 32, 0);
252 setRegMask(MISCREG_CONFIG3
, cfg3_Mask
);
255 EBaseReg eBase
= readMiscRegNoEffect(MISCREG_EBASE
);
256 eBase
.cpuNum
= cp
.CP0_EBase_CPUNum
;
257 replaceBits(eBase
, 31, 31, 1);
258 setMiscRegNoEffect(MISCREG_EBASE
, eBase
);
259 // Now, create Write Mask for Config register
260 MiscReg EB_Mask
= 0x3FFFF000;// Except Exception Base, the
261 // entire register is read only
262 replaceBits(EB_Mask
, 0, 32, 0);
263 setRegMask(MISCREG_EBASE
, EB_Mask
);
265 // SRS Control - HSS (Highest Shadow Set)
266 SRSCtlReg scsCtl
= readMiscRegNoEffect(MISCREG_SRSCTL
);
267 scsCtl
.hss
= cp
.CP0_SrsCtl_HSS
;
268 setMiscRegNoEffect(MISCREG_SRSCTL
, scsCtl
);
269 // Now, create Write Mask for the SRS Ctl register
270 MiscReg SC_Mask
= 0x0000F3C0;
271 replaceBits(SC_Mask
, 0, 32, 0);
272 setRegMask(MISCREG_SRSCTL
, SC_Mask
);
274 // IntCtl - IPTI, IPPCI
275 IntCtlReg intCtl
= readMiscRegNoEffect(MISCREG_INTCTL
);
276 intCtl
.ipti
= cp
.CP0_IntCtl_IPTI
;
277 intCtl
.ippci
= cp
.CP0_IntCtl_IPPCI
;
278 setMiscRegNoEffect(MISCREG_INTCTL
, intCtl
);
279 // Now, create Write Mask for the IntCtl register
280 MiscReg IC_Mask
= 0x000003E0;
281 replaceBits(IC_Mask
, 0, 32, 0);
282 setRegMask(MISCREG_INTCTL
, IC_Mask
);
284 // Watch Hi - M - FIXME (More than 1 Watch register)
285 WatchHiReg watchHi
= readMiscRegNoEffect(MISCREG_WATCHHI0
);
286 watchHi
.m
= cp
.CP0_WatchHi_M
;
287 setMiscRegNoEffect(MISCREG_WATCHHI0
, watchHi
);
288 // Now, create Write Mask for the IntCtl register
289 MiscReg wh_Mask
= 0x7FFF0FFF;
290 replaceBits(wh_Mask
, 0, 32, 0);
291 setRegMask(MISCREG_WATCHHI0
, wh_Mask
);
293 // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
294 PerfCntCtlReg perfCntCtl
= readMiscRegNoEffect(MISCREG_PERFCNT0
);
295 perfCntCtl
.m
= cp
.CP0_PerfCtr_M
;
296 perfCntCtl
.w
= cp
.CP0_PerfCtr_W
;
297 setMiscRegNoEffect(MISCREG_PERFCNT0
, perfCntCtl
);
298 // Now, create Write Mask for the IntCtl register
299 MiscReg pc_Mask
= 0x00007FF;
300 replaceBits(pc_Mask
, 0, 32, 0);
301 setRegMask(MISCREG_PERFCNT0
, pc_Mask
);
304 setMiscRegNoEffect(MISCREG_CP0_RANDOM
, 63);
305 // Now, create Write Mask for the IntCtl register
306 MiscReg random_Mask
= 0;
307 replaceBits(random_Mask
, 0, 32, 0);
308 setRegMask(MISCREG_CP0_RANDOM
, random_Mask
);
311 PageGrainReg pageGrain
= readMiscRegNoEffect(MISCREG_PAGEGRAIN
);
312 pageGrain
.esp
= cp
.CP0_Config3_SP
;
313 setMiscRegNoEffect(MISCREG_PAGEGRAIN
, pageGrain
);
314 // Now, create Write Mask for the IntCtl register
315 MiscReg pg_Mask
= 0x10000000;
316 replaceBits(pg_Mask
, 0, 32, 0);
317 setRegMask(MISCREG_PAGEGRAIN
, pg_Mask
);
320 StatusReg status
= readMiscRegNoEffect(MISCREG_STATUS
);
321 // Only CU0 and IE are modified on a reset - everything else needs
322 // to be controlled on a per CPU model basis
324 // Enable CP0 on reset
327 // Enable ERL bit on a reset
329 // Enable BEV bit on a reset
332 setMiscRegNoEffect(MISCREG_STATUS
, status
);
333 // Now, create Write Mask for the Status register
334 MiscReg stat_Mask
= 0xFF78FF17;
335 replaceBits(stat_Mask
, 0, 32, 0);
336 setRegMask(MISCREG_STATUS
, stat_Mask
);
340 MVPConf0Reg mvpConf0
= readMiscRegNoEffect(MISCREG_MVP_CONF0
);
342 mvpConf0
.pvpe
= numVpes
- 1;
343 mvpConf0
.ptc
= numThreads
- 1;
344 setMiscRegNoEffect(MISCREG_MVP_CONF0
, mvpConf0
);
347 VPEConf0Reg vpeConf0
= readMiscRegNoEffect(MISCREG_VPE_CONF0
);
349 setMiscRegNoEffect(MISCREG_VPE_CONF0
, vpeConf0
);
352 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
353 TCBindReg tcBind
= readMiscRegNoEffect(MISCREG_TC_BIND
, tid
);
355 setMiscRegNoEffect(MISCREG_TC_BIND
, tcBind
, tid
);
358 TCHaltReg tcHalt
= readMiscRegNoEffect(MISCREG_TC_HALT
);
360 setMiscRegNoEffect(MISCREG_TC_HALT
, tcHalt
);
363 // Set TCStatus Activated to 1 for the initial thread that is running
364 TCStatusReg tcStatus
= readMiscRegNoEffect(MISCREG_TC_STATUS
);
366 setMiscRegNoEffect(MISCREG_TC_STATUS
, tcStatus
);
368 // Set Dynamically Allocatable bit to 1 for all other threads
369 for (ThreadID tid
= 1; tid
< numThreads
; tid
++) {
370 tcStatus
= readMiscRegNoEffect(MISCREG_TC_STATUS
, tid
);
372 setMiscRegNoEffect(MISCREG_TC_STATUS
, tcStatus
, tid
);
376 MiscReg mask
= 0x7FFFFFFF;
378 // Now, create Write Mask for the Index register
379 replaceBits(mask
, 0, 32, 0);
380 setRegMask(MISCREG_INDEX
, mask
);
383 replaceBits(mask
, 0, 32, 0);
384 setRegMask(MISCREG_ENTRYLO0
, mask
);
385 setRegMask(MISCREG_ENTRYLO1
, mask
);
388 replaceBits(mask
, 0, 32, 0);
389 setRegMask(MISCREG_CONTEXT
, mask
);
392 replaceBits(mask
, 0, 32, 0);
393 setRegMask(MISCREG_PAGEMASK
, mask
);
396 replaceBits(mask
, 0, 32, 0);
397 setRegMask(MISCREG_BADVADDR
, mask
);
398 setRegMask(MISCREG_LLADDR
, mask
);
401 replaceBits(mask
, 0, 32, 0);
402 setRegMask(MISCREG_CAUSE
, mask
);
407 ISA::getVPENum(ThreadID tid
)
409 TCBindReg tcBind
= miscRegFile
[MISCREG_TC_BIND
][tid
];
410 return tcBind
.curVPE
;
414 ISA::readMiscRegNoEffect(int misc_reg
, ThreadID tid
)
416 unsigned reg_sel
= (bankType
[misc_reg
] == perThreadContext
)
417 ? tid
: getVPENum(tid
);
418 DPRINTF(MipsPRA
, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
419 misc_reg
/ 8, misc_reg
% 8, miscRegNames
[misc_reg
],
420 miscRegFile
[misc_reg
][reg_sel
]);
421 return miscRegFile
[misc_reg
][reg_sel
];
424 //@TODO: MIPS MT's register view automatically connects
425 // Status to TCStatus depending on current thread
426 //template <class TC>
428 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
, ThreadID tid
)
430 unsigned reg_sel
= (bankType
[misc_reg
] == perThreadContext
)
431 ? tid
: getVPENum(tid
);
433 "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
434 misc_reg
/ 8, misc_reg
% 8, miscRegNames
[misc_reg
],
435 miscRegFile
[misc_reg
][reg_sel
]);
437 return miscRegFile
[misc_reg
][reg_sel
];
441 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
443 unsigned reg_sel
= (bankType
[misc_reg
] == perThreadContext
)
444 ? tid
: getVPENum(tid
);
446 "[tid:%i]: Setting (direct set) CP0 Register:%u "
447 "Select:%u (%s) to %#x.\n",
448 tid
, misc_reg
/ 8, misc_reg
% 8, miscRegNames
[misc_reg
], val
);
450 miscRegFile
[misc_reg
][reg_sel
] = val
;
454 ISA::setRegMask(int misc_reg
, const MiscReg
&val
, ThreadID tid
)
456 unsigned reg_sel
= (bankType
[misc_reg
] == perThreadContext
)
457 ? tid
: getVPENum(tid
);
459 "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
460 tid
, misc_reg
/ 8, misc_reg
% 8, miscRegNames
[misc_reg
], val
);
461 miscRegFile_WriteMask
[misc_reg
][reg_sel
] = val
;
464 // PROGRAMMER'S NOTES:
465 // (1) Some CP0 Registers have fields that cannot
466 // be overwritten. Make sure to handle those particular registers
469 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
,
470 ThreadContext
*tc
, ThreadID tid
)
472 int reg_sel
= (bankType
[misc_reg
] == perThreadContext
)
473 ? tid
: getVPENum(tid
);
476 "[tid:%i]: Setting CP0 Register:%u "
477 "Select:%u (%s) to %#x, with effect.\n",
478 tid
, misc_reg
/ 8, misc_reg
% 8, miscRegNames
[misc_reg
], val
);
480 MiscReg cp0_val
= filterCP0Write(misc_reg
, reg_sel
, val
);
482 miscRegFile
[misc_reg
][reg_sel
] = cp0_val
;
484 scheduleCP0Update(tc
->getCpuPtr(), 1);
488 * This method doesn't need to adjust the Control Register Offset
489 * since it has already been done in the calling method
493 ISA::filterCP0Write(int misc_reg
, int reg_sel
, const MiscReg
&val
)
495 MiscReg retVal
= val
;
497 // Mask off read-only regions
498 retVal
&= miscRegFile_WriteMask
[misc_reg
][reg_sel
];
499 MiscReg curVal
= miscRegFile
[misc_reg
][reg_sel
];
500 // Mask off current alue with inverse mask (clear writeable bits)
501 curVal
&= (~miscRegFile_WriteMask
[misc_reg
][reg_sel
]);
502 retVal
|= curVal
; // Combine the two
504 "filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
505 "current val: %lx, written val: %x\n",
506 miscRegFile_WriteMask
[misc_reg
][reg_sel
],
507 ~miscRegFile_WriteMask
[misc_reg
][reg_sel
],
508 val
, miscRegFile
[misc_reg
][reg_sel
], retVal
);
513 ISA::scheduleCP0Update(BaseCPU
*cpu
, int delay
)
519 CP0Event
*cp0_event
= new CP0Event(this, cpu
, UpdateCP0
);
520 cpu
->schedule(cp0_event
, curTick() + cpu
->ticks(delay
));
525 ISA::updateCPU(BaseCPU
*cpu
)
527 ///////////////////////////////////////////////////////////////////
529 // EVALUATE CP0 STATE FOR MIPS MT
531 ///////////////////////////////////////////////////////////////////
532 MVPConf0Reg mvpConf0
= readMiscRegNoEffect(MISCREG_MVP_CONF0
);
533 ThreadID num_threads
= mvpConf0
.ptc
+ 1;
535 for (ThreadID tid
= 0; tid
< num_threads
; tid
++) {
536 TCStatusReg tcStatus
= readMiscRegNoEffect(MISCREG_TC_STATUS
, tid
);
537 TCHaltReg tcHalt
= readMiscRegNoEffect(MISCREG_TC_HALT
, tid
);
539 //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
540 if (tcHalt
.h
== 1 || tcStatus
.a
== 0) {
541 haltThread(cpu
->getContext(tid
));
542 } else if (tcHalt
.h
== 0 && tcStatus
.a
== 1) {
543 restoreThread(cpu
->getContext(tid
));
547 num_threads
= mvpConf0
.ptc
+ 1;
549 // Toggle update flag after we finished updating
553 ISA::CP0Event::CP0Event(CP0
*_cp0
, BaseCPU
*_cpu
, CP0EventType e_type
)
554 : Event(CPU_Tick_Pri
), cp0(_cp0
), cpu(_cpu
), cp0EventType(e_type
)
558 ISA::CP0Event::process()
560 switch (cp0EventType
)
569 ISA::CP0Event::description() const
571 return "Coprocessor-0 event";
575 ISA::CP0Event::scheduleEvent(int delay
)
577 cpu
->reschedule(this, curTick() + cpu
->ticks(delay
), true);
581 ISA::CP0Event::unscheduleEvent()