src/arch/mips/isa.hh

   1 /*
   2  * Copyright (c) 2009 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_MIPS_ISA_HH__
  30 #define __ARCH_MIPS_ISA_HH__
  31
  32 #include <queue>
  33 #include <string>
  34 #include <vector>
  35
  36 #include "arch/generic/isa.hh"
  37 #include "arch/mips/registers.hh"
  38 #include "arch/mips/types.hh"
  39 #include "cpu/reg_class.hh"
  40 #include "sim/eventq.hh"
  41 #include "sim/sim_object.hh"
  42
  43 class BaseCPU;
  44 class Checkpoint;
  45 class EventManager;
  46 struct MipsISAParams;
  47 class ThreadContext;
  48
  49 namespace MipsISA
  50 {
  51     class ISA : public BaseISA
  52     {
  53       public:
  54         // The MIPS name for this file is CP0 or Coprocessor 0
  55         typedef ISA CP0;
  56
  57         typedef MipsISAParams Params;
  58
  59       protected:
  60         // Number of threads and vpes an individual ISA state can handle
  61         uint8_t numThreads;
  62         uint8_t numVpes;
  63
  64         enum BankType {
  65             perProcessor,
  66             perThreadContext,
  67             perVirtProcessor
  68         };
  69
  70         std::vector<std::vector<RegVal> > miscRegFile;
  71         std::vector<std::vector<RegVal> > miscRegFile_WriteMask;
  72         std::vector<BankType> bankType;
  73
  74       public:
  75         void clear();
  76
  77         void configCP();
  78
  79         unsigned getVPENum(ThreadID tid) const;
  80
  81         //////////////////////////////////////////////////////////
  82         //
  83         // READ/WRITE CP0 STATE
  84         //
  85         //
  86         //////////////////////////////////////////////////////////
  87         //@TODO: MIPS MT's register view automatically connects
  88         //       Status to TCStatus depending on current thread
  89         void updateCP0ReadView(int misc_reg, ThreadID tid) { }
  90         RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
  91
  92         //template <class TC>
  93         RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
  94
  95         RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val);
  96         void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0);
  97         void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
  98
  99         //template <class TC>
 100         void setMiscReg(int misc_reg, RegVal val,
 101                         ThreadContext *tc, ThreadID tid=0);
 102
 103         //////////////////////////////////////////////////////////
 104         //
 105         // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
 106         // TO SCHEDULE EVENTS
 107         //
 108         //////////////////////////////////////////////////////////
 109
 110         // Flag that is set when CP0 state has been written to.
 111         bool cp0Updated;
 112
 113         // Enumerated List of CP0 Event Types
 114         enum CP0EventType {
 115             UpdateCP0
 116         };
 117
 118         /** Process a CP0 event */
 119         void processCP0Event(BaseCPU *cpu, CP0EventType);
 120
 121         // Schedule a CP0 Update Event
 122         void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
 123
 124         // If any changes have been made, then check the state for changes
 125         // and if necessary alert the CPU
 126         void updateCPU(BaseCPU *cpu);
 127
 128         static std::string miscRegNames[NumMiscRegs];
 129
 130       public:
 131         void startup(ThreadContext *tc) {}
 132
 133         /// Explicitly import the otherwise hidden startup
 134         using BaseISA::startup;
 135
 136         const Params *params() const;
 137
 138         ISA(Params *p);
 139
 140         RegId flattenRegId(const RegId& regId) const { return regId; }
 141
 142         int
 143         flattenIntIndex(int reg) const
 144         {
 145             return reg;
 146         }
 147
 148         int
 149         flattenFloatIndex(int reg) const
 150         {
 151             return reg;
 152         }
 153
 154         int
 155         flattenVecIndex(int reg) const
 156         {
 157             return reg;
 158         }
 159
 160         int
 161         flattenVecElemIndex(int reg) const
 162         {
 163             return reg;
 164         }
 165
 166         int
 167         flattenVecPredIndex(int reg) const
 168         {
 169             return reg;
 170         }
 171
 172         // dummy
 173         int
 174         flattenCCIndex(int reg) const
 175         {
 176             return reg;
 177         }
 178
 179         int
 180         flattenMiscIndex(int reg) const
 181         {
 182             return reg;
 183         }
 184
 185     };
 186 }
 187
 188 #endif