src/arch/mips/isa.hh

   1 /*
   2  * Copyright (c) 2009 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_MIPS_ISA_HH__
  32 #define __ARCH_MIPS_ISA_HH__
  33
  34 #include <queue>
  35 #include <string>
  36 #include <vector>
  37
  38 #include "arch/generic/isa.hh"
  39 #include "arch/mips/registers.hh"
  40 #include "arch/mips/types.hh"
  41 #include "cpu/reg_class.hh"
  42 #include "sim/eventq.hh"
  43 #include "sim/sim_object.hh"
  44
  45 class BaseCPU;
  46 class Checkpoint;
  47 class EventManager;
  48 struct MipsISAParams;
  49 class ThreadContext;
  50
  51 namespace MipsISA
  52 {
  53     class ISA : public BaseISA
  54     {
  55       public:
  56         // The MIPS name for this file is CP0 or Coprocessor 0
  57         typedef ISA CP0;
  58
  59         typedef MipsISAParams Params;
  60
  61       protected:
  62         // Number of threads and vpes an individual ISA state can handle
  63         uint8_t numThreads;
  64         uint8_t numVpes;
  65
  66         enum BankType {
  67             perProcessor,
  68             perThreadContext,
  69             perVirtProcessor
  70         };
  71
  72         std::vector<std::vector<RegVal> > miscRegFile;
  73         std::vector<std::vector<RegVal> > miscRegFile_WriteMask;
  74         std::vector<BankType> bankType;
  75
  76       public:
  77         void clear();
  78
  79         void configCP();
  80
  81         unsigned getVPENum(ThreadID tid) const;
  82
  83         //////////////////////////////////////////////////////////
  84         //
  85         // READ/WRITE CP0 STATE
  86         //
  87         //
  88         //////////////////////////////////////////////////////////
  89         //@TODO: MIPS MT's register view automatically connects
  90         //       Status to TCStatus depending on current thread
  91         void updateCP0ReadView(int misc_reg, ThreadID tid) { }
  92         RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
  93
  94         //template <class TC>
  95         RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
  96
  97         RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val);
  98         void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0);
  99         void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
 100
 101         //template <class TC>
 102         void setMiscReg(int misc_reg, RegVal val,
 103                         ThreadContext *tc, ThreadID tid=0);
 104
 105         //////////////////////////////////////////////////////////
 106         //
 107         // DECLARE INTERFACE THAT WILL ALLOW A MiscRegFile (Cop0)
 108         // TO SCHEDULE EVENTS
 109         //
 110         //////////////////////////////////////////////////////////
 111
 112         // Flag that is set when CP0 state has been written to.
 113         bool cp0Updated;
 114
 115         // Enumerated List of CP0 Event Types
 116         enum CP0EventType {
 117             UpdateCP0
 118         };
 119
 120         /** Process a CP0 event */
 121         void processCP0Event(BaseCPU *cpu, CP0EventType);
 122
 123         // Schedule a CP0 Update Event
 124         void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
 125
 126         // If any changes have been made, then check the state for changes
 127         // and if necessary alert the CPU
 128         void updateCPU(BaseCPU *cpu);
 129
 130         static std::string miscRegNames[NumMiscRegs];
 131
 132       public:
 133         void startup(ThreadContext *tc) {}
 134
 135         /// Explicitly import the otherwise hidden startup
 136         using BaseISA::startup;
 137
 138         const Params *params() const;
 139
 140         ISA(Params *p);
 141
 142         RegId flattenRegId(const RegId& regId) const { return regId; }
 143
 144         int
 145         flattenIntIndex(int reg) const
 146         {
 147             return reg;
 148         }
 149
 150         int
 151         flattenFloatIndex(int reg) const
 152         {
 153             return reg;
 154         }
 155
 156         int
 157         flattenVecIndex(int reg) const
 158         {
 159             return reg;
 160         }
 161
 162         int
 163         flattenVecElemIndex(int reg) const
 164         {
 165             return reg;
 166         }
 167
 168         int
 169         flattenVecPredIndex(int reg) const
 170         {
 171             return reg;
 172         }
 173
 174         // dummy
 175         int
 176         flattenCCIndex(int reg) const
 177         {
 178             return reg;
 179         }
 180
 181         int
 182         flattenMiscIndex(int reg) const
 183         {
 184             return reg;
 185         }
 186
 187     };
 188 }
 189
 190 #endif