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3 * Copyright (c) 2007 MIPS Technologies, Inc.
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34 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
35 #define __ARCH_MIPS_ISA_TRAITS_HH__
37 #include "arch/mips/types.hh"
38 #include "arch/mips/mips_core_specific.hh"
39 #include "config/full_system.hh"
40 #include "sim/host.hh"
42 namespace LittleEndianGuest {};
50 using namespace LittleEndianGuest;
52 StaticInstPtr decodeInst(ExtMachInst);
54 // MIPS DOES have a delay slot
55 #define ISA_HAS_DELAY_SLOT 1
57 const Addr PageShift = 13;
58 const Addr PageBytes = ULL(1) << PageShift;
59 const Addr Page_Mask = ~(PageBytes - 1);
60 const Addr PageOffset = PageBytes - 1;
63 ////////////////////////////////////////////////////////////////////////
68 const Addr PteShift = 3;
69 const Addr NPtePageShift = PageShift - PteShift;
70 const Addr NPtePage = ULL(1) << NPtePageShift;
71 const Addr PteMask = NPtePage - 1;
73 //// All 'Mapped' segments go through the TLB
74 //// All other segments are translated by dropping the MSB, to give
75 //// the corresponding physical address
76 // User Segment - Mapped
77 const Addr USegBase = ULL(0x0);
78 const Addr USegEnd = ULL(0x7FFFFFFF);
80 // Kernel Segment 0 - Unmapped
81 const Addr KSeg0End = ULL(0x9FFFFFFF);
82 const Addr KSeg0Base = ULL(0x80000000);
83 const Addr KSeg0Mask = ULL(0x1FFFFFFF);
85 // Kernel Segment 1 - Unmapped, Uncached
86 const Addr KSeg1End = ULL(0xBFFFFFFF);
87 const Addr KSeg1Base = ULL(0xA0000000);
88 const Addr KSeg1Mask = ULL(0x1FFFFFFF);
90 // Kernel/Supervisor Segment - Mapped
91 const Addr KSSegEnd = ULL(0xDFFFFFFF);
92 const Addr KSSegBase = ULL(0xC0000000);
94 // Kernel Segment 3 - Mapped
95 const Addr KSeg3End = ULL(0xFFFFFFFF);
96 const Addr KSeg3Base = ULL(0xE0000000);
99 // For loading... XXX This maybe could be USegEnd?? --ali
100 const Addr LoadAddrMask = ULL(0xffffffffff);
102 inline Addr Phys2K0Seg(Addr addr)
104 // if (addr & PAddrUncachedBit43) {
105 // addr &= PAddrUncachedMask;
106 // addr |= PAddrUncachedBit40;
108 return addr | KSeg0Base;
112 const unsigned VABits = 32;
113 const unsigned PABits = 32; // Is this correct?
114 const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
115 const Addr VAddrUnImplMask = ~VAddrImplMask;
116 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
117 inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
118 inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
120 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
122 ////////////////////////////////////////////////////////////////////////
128 INTLEVEL_SOFTWARE_MIN = 4,
129 INTLEVEL_SOFTWARE_MAX = 19,
131 INTLEVEL_EXTERNAL_MIN = 20,
132 INTLEVEL_EXTERNAL_MAX = 34,
136 INTINDEX_ETHERNET = 0,
141 INTLEVEL_SERIAL = 33,
143 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
150 mode_kernel = 0, // kernel
151 mode_supervisor = 1, // supervisor
152 mode_user = 2, // user mode
153 mode_debug = 3, // debug mode
154 mode_number // number of modes
157 inline mode_type getOperatingMode(MiscReg Stat)
159 if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
162 if((Stat & 0x18) == 0x8)
163 return mode_supervisor;
164 else if((Stat & 0x18) == 0x10)
166 else return mode_number;
171 // return a no-op instruction... used for instruction fetch faults
172 const ExtMachInst NoopMachInst = 0x00000000;
174 // Constants Related to the number of registers
175 const int NumIntArchRegs = 32;
176 const int NumIntSpecialRegs = 9;
177 const int NumFloatArchRegs = 32;
178 const int NumFloatSpecialRegs = 5;
180 const int NumShadowRegSets = 16; // Maximum number of shadow register sets
181 const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs
182 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
184 const int TotalArchRegs = NumIntArchRegs * NumShadowRegSets;
186 // Static instruction parameters
187 const int MaxInstSrcRegs = 10;
188 const int MaxInstDestRegs = 8;
190 // semantically meaningful register indices
191 const int ZeroReg = 0;
192 const int AssemblerReg = 1;
193 const int ReturnValueReg = 2;
194 const int ReturnValueReg1 = 2;
195 const int ReturnValueReg2 = 3;
196 const int ArgumentReg0 = 4;
197 const int ArgumentReg1 = 5;
198 const int ArgumentReg2 = 6;
199 const int ArgumentReg3 = 7;
200 const int KernelReg0 = 26;
201 const int KernelReg1 = 27;
202 const int GlobalPointerReg = 28;
203 const int StackPointerReg = 29;
204 const int FramePointerReg = 30;
205 const int ReturnAddressReg = 31;
207 const int ArgumentReg[] = {4, 5, 6, 7};
208 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
210 const int SyscallNumReg = ReturnValueReg1;
211 const int SyscallPseudoReturnReg = ReturnValueReg2;
212 const int SyscallSuccessReg = ArgumentReg3;
214 const int LogVMPageSize = 13; // 8K bytes
215 const int VMPageSize = (1 << LogVMPageSize);
217 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
219 const int MachineBytes = 4;
220 const int WordBytes = 4;
221 const int HalfwordBytes = 2;
222 const int ByteBytes = 1;
224 const int ANNOTE_NONE = 0;
225 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
227 // These help enumerate all the registers for dependence tracking.
228 const int FP_Base_DepTag = NumIntRegs;
229 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
231 // Enumerate names for 'Control' Registers in the CPU
232 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
233 // (Register Number-Register Select) Summary of Register
234 //------------------------------------------------------
235 // The first set of names classify the CP0 names as Register Banks
236 // for easy indexing when using the 'RD + SEL' index combination
237 // in CP0 instructions.
239 Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3
244 CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15
253 EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23
262 EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24
264 Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33
267 PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
268 PageGrain = Ctrl_Base_DepTag + 41,
270 Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55
277 HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63
279 BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71
281 Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79
283 EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87
285 Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95
287 Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103
292 Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111
294 EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119
296 PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127,
299 Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135
309 LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143
311 WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151
320 WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159
329 XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
335 Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191
341 DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199
343 PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207
352 ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215
354 CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223
359 TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231
368 TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239
378 ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247
380 DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256
382 LLFlag = Ctrl_Base_DepTag + 257,
387 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
389 const int NumMiscRegs = NumControlRegs;
391 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
396 using namespace MipsISA;
398 #endif // __ARCH_MIPS_ISA_TRAITS_HH__