src/arch/mips/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Gabe Black
  30  *          Korey Sewell
  31  *          Jaidev Patwardhan
  32  */
  33
  34 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
  35 #define __ARCH_MIPS_ISA_TRAITS_HH__
  36
  37 #include "arch/mips/types.hh"
  38 #include "arch/mips/mips_core_specific.hh"
  39 #include "base/types.hh"
  40 #include "config/full_system.hh"
  41
  42 namespace LittleEndianGuest {};
  43
  44 #define TARGET_MIPS
  45
  46 class StaticInstPtr;
  47
  48 namespace MipsISA
  49 {
  50     using namespace LittleEndianGuest;
  51
  52     StaticInstPtr decodeInst(ExtMachInst);
  53
  54     // MIPS DOES have a delay slot
  55     #define ISA_HAS_DELAY_SLOT 1
  56
  57     const Addr PageShift = 13;
  58     const Addr PageBytes = ULL(1) << PageShift;
  59     const Addr Page_Mask = ~(PageBytes - 1);
  60     const Addr PageOffset = PageBytes - 1;
  61
  62
  63     ////////////////////////////////////////////////////////////////////////
  64     //
  65     //  Translation stuff
  66     //
  67
  68     const Addr PteShift = 3;
  69     const Addr NPtePageShift = PageShift - PteShift;
  70     const Addr NPtePage = ULL(1) << NPtePageShift;
  71     const Addr PteMask = NPtePage - 1;
  72
  73     //// All 'Mapped' segments go through the TLB
  74     //// All other segments are translated by dropping the MSB, to give
  75     //// the corresponding physical address
  76     // User Segment - Mapped
  77     const Addr USegBase = ULL(0x0);
  78     const Addr USegEnd = ULL(0x7FFFFFFF);
  79
  80     // Kernel Segment 0 - Unmapped
  81     const Addr KSeg0End = ULL(0x9FFFFFFF);
  82     const Addr KSeg0Base =  ULL(0x80000000);
  83     const Addr KSeg0Mask = ULL(0x1FFFFFFF);
  84
  85     // Kernel Segment 1 - Unmapped, Uncached
  86     const Addr KSeg1End = ULL(0xBFFFFFFF);
  87     const Addr KSeg1Base = ULL(0xA0000000);
  88     const Addr KSeg1Mask = ULL(0x1FFFFFFF);
  89
  90     // Kernel/Supervisor Segment - Mapped
  91     const Addr KSSegEnd = ULL(0xDFFFFFFF);
  92     const Addr KSSegBase = ULL(0xC0000000);
  93
  94     // Kernel Segment 3 - Mapped
  95     const Addr KSeg3End = ULL(0xFFFFFFFF);
  96     const Addr KSeg3Base = ULL(0xE0000000);
  97
  98
  99     // For loading... XXX This maybe could be USegEnd?? --ali
 100     const Addr LoadAddrMask = ULL(0xffffffffff);
 101
 102     inline Addr Phys2K0Seg(Addr addr)
 103     {
 104    //  if (addr & PAddrUncachedBit43) {
 105 //         addr &= PAddrUncachedMask;
 106 //         addr |= PAddrUncachedBit40;
 107 //     }
 108         return addr | KSeg0Base;
 109     }
 110
 111
 112     const unsigned VABits = 32;
 113     const unsigned PABits = 32; // Is this correct?
 114     const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
 115     const Addr VAddrUnImplMask = ~VAddrImplMask;
 116     inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
 117     inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
 118     inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
 119
 120     const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
 121
 122     ////////////////////////////////////////////////////////////////////////
 123     //
 124     //  Interrupt levels
 125     //
 126     enum InterruptLevels
 127     {
 128         INTLEVEL_SOFTWARE_MIN = 4,
 129         INTLEVEL_SOFTWARE_MAX = 19,
 130
 131         INTLEVEL_EXTERNAL_MIN = 20,
 132         INTLEVEL_EXTERNAL_MAX = 34,
 133
 134         INTLEVEL_IRQ0 = 20,
 135         INTLEVEL_IRQ1 = 21,
 136         INTINDEX_ETHERNET = 0,
 137         INTINDEX_SCSI = 1,
 138         INTLEVEL_IRQ2 = 22,
 139         INTLEVEL_IRQ3 = 23,
 140
 141         INTLEVEL_SERIAL = 33,
 142
 143         NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
 144     };
 145
 146     // MIPS modes
 147     enum mode_type
 148     {
 149         mode_kernel = 0,        // kernel
 150         mode_supervisor = 1,    // supervisor
 151         mode_user = 2,          // user mode
 152         mode_debug = 3,         // debug mode
 153         mode_number             // number of modes
 154     };
 155
 156     // return a no-op instruction... used for instruction fetch faults
 157     const ExtMachInst NoopMachInst = 0x00000000;
 158
 159     const int LogVMPageSize = 13;       // 8K bytes
 160     const int VMPageSize = (1 << LogVMPageSize);
 161
 162     const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
 163
 164     const int MachineBytes = 4;
 165     const int WordBytes = 4;
 166     const int HalfwordBytes = 2;
 167     const int ByteBytes = 1;
 168
 169     const int ANNOTE_NONE = 0;
 170     const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 171 };
 172
 173 #endif // __ARCH_MIPS_ISA_TRAITS_HH__