src/arch/mips/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Gabe Black
  30  *          Korey Sewell
  31  *          Jaidev Patwardhan
  32  */
  33
  34 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
  35 #define __ARCH_MIPS_ISA_TRAITS_HH__
  36
  37 #include "arch/mips/types.hh"
  38 #include "base/types.hh"
  39 #include "cpu/static_inst_fwd.hh"
  40
  41 namespace LittleEndianGuest {}
  42
  43 namespace MipsISA
  44 {
  45
  46 using namespace LittleEndianGuest;
  47
  48 StaticInstPtr decodeInst(ExtMachInst);
  49
  50 // MIPS DOES have a delay slot
  51 #define ISA_HAS_DELAY_SLOT 1
  52
  53 const Addr PageShift = 13;
  54 const Addr PageBytes = ULL(1) << PageShift;
  55 const Addr Page_Mask = ~(PageBytes - 1);
  56 const Addr PageOffset = PageBytes - 1;
  57
  58
  59 ////////////////////////////////////////////////////////////////////////
  60 //
  61 //  Translation stuff
  62 //
  63
  64 const Addr PteShift = 3;
  65 const Addr NPtePageShift = PageShift - PteShift;
  66 const Addr NPtePage = ULL(1) << NPtePageShift;
  67 const Addr PteMask = NPtePage - 1;
  68
  69 //// All 'Mapped' segments go through the TLB
  70 //// All other segments are translated by dropping the MSB, to give
  71 //// the corresponding physical address
  72 // User Segment - Mapped
  73 const Addr USegBase = ULL(0x0);
  74 const Addr USegEnd = ULL(0x7FFFFFFF);
  75
  76 // Kernel Segment 0 - Unmapped
  77 const Addr KSeg0End = ULL(0x9FFFFFFF);
  78 const Addr KSeg0Base =  ULL(0x80000000);
  79 const Addr KSeg0Mask = ULL(0x1FFFFFFF);
  80
  81 // Kernel Segment 1 - Unmapped, Uncached
  82 const Addr KSeg1End = ULL(0xBFFFFFFF);
  83 const Addr KSeg1Base = ULL(0xA0000000);
  84 const Addr KSeg1Mask = ULL(0x1FFFFFFF);
  85
  86 // Kernel/Supervisor Segment - Mapped
  87 const Addr KSSegEnd = ULL(0xDFFFFFFF);
  88 const Addr KSSegBase = ULL(0xC0000000);
  89
  90 // Kernel Segment 3 - Mapped
  91 const Addr KSeg3End = ULL(0xFFFFFFFF);
  92 const Addr KSeg3Base = ULL(0xE0000000);
  93
  94
  95 inline Addr Phys2K0Seg(Addr addr)
  96 {
  97     return addr | KSeg0Base;
  98 }
  99
 100
 101 const unsigned VABits = 32;
 102 const unsigned PABits = 32; // Is this correct?
 103 const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
 104 const Addr VAddrUnImplMask = ~VAddrImplMask;
 105 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
 106 inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
 107 inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
 108
 109 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
 110
 111 ////////////////////////////////////////////////////////////////////////
 112 //
 113 //  Interrupt levels
 114 //
 115 enum InterruptLevels
 116 {
 117     INTLEVEL_SOFTWARE_MIN = 4,
 118     INTLEVEL_SOFTWARE_MAX = 19,
 119
 120     INTLEVEL_EXTERNAL_MIN = 20,
 121     INTLEVEL_EXTERNAL_MAX = 34,
 122
 123     INTLEVEL_IRQ0 = 20,
 124     INTLEVEL_IRQ1 = 21,
 125     INTINDEX_ETHERNET = 0,
 126     INTINDEX_SCSI = 1,
 127     INTLEVEL_IRQ2 = 22,
 128     INTLEVEL_IRQ3 = 23,
 129
 130     INTLEVEL_SERIAL = 33,
 131
 132     NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
 133 };
 134
 135 // MIPS modes
 136 enum mode_type
 137 {
 138     mode_kernel = 0,        // kernel
 139     mode_supervisor = 1,    // supervisor
 140     mode_user = 2,          // user mode
 141     mode_debug = 3,         // debug mode
 142     mode_number             // number of modes
 143 };
 144
 145 // return a no-op instruction... used for instruction fetch faults
 146 const ExtMachInst NoopMachInst = 0x00000000;
 147
 148 const int ANNOTE_NONE = 0;
 149 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 150
 151 const bool HasUnalignedMemAcc = true;
 152
 153 const bool CurThreadInfoImplemented = false;
 154 const int CurThreadInfoReg = -1;
 155
 156 } // namespace MipsISA
 157
 158 #endif // __ARCH_MIPS_ISA_TRAITS_HH__