2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
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34 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
35 #define __ARCH_MIPS_ISA_TRAITS_HH__
37 #include "arch/mips/types.hh"
38 #include "base/types.hh"
39 #include "cpu/static_inst_fwd.hh"
41 namespace LittleEndianGuest {}
46 using namespace LittleEndianGuest;
48 StaticInstPtr decodeInst(ExtMachInst);
50 // MIPS DOES have a delay slot
51 #define ISA_HAS_DELAY_SLOT 1
53 const Addr PageShift = 13;
54 const Addr PageBytes = ULL(1) << PageShift;
55 const Addr Page_Mask = ~(PageBytes - 1);
56 const Addr PageOffset = PageBytes - 1;
59 ////////////////////////////////////////////////////////////////////////
64 const Addr PteShift = 3;
65 const Addr NPtePageShift = PageShift - PteShift;
66 const Addr NPtePage = ULL(1) << NPtePageShift;
67 const Addr PteMask = NPtePage - 1;
69 //// All 'Mapped' segments go through the TLB
70 //// All other segments are translated by dropping the MSB, to give
71 //// the corresponding physical address
72 // User Segment - Mapped
73 const Addr USegBase = ULL(0x0);
74 const Addr USegEnd = ULL(0x7FFFFFFF);
76 // Kernel Segment 0 - Unmapped
77 const Addr KSeg0End = ULL(0x9FFFFFFF);
78 const Addr KSeg0Base = ULL(0x80000000);
79 const Addr KSeg0Mask = ULL(0x1FFFFFFF);
81 // Kernel Segment 1 - Unmapped, Uncached
82 const Addr KSeg1End = ULL(0xBFFFFFFF);
83 const Addr KSeg1Base = ULL(0xA0000000);
84 const Addr KSeg1Mask = ULL(0x1FFFFFFF);
86 // Kernel/Supervisor Segment - Mapped
87 const Addr KSSegEnd = ULL(0xDFFFFFFF);
88 const Addr KSSegBase = ULL(0xC0000000);
90 // Kernel Segment 3 - Mapped
91 const Addr KSeg3End = ULL(0xFFFFFFFF);
92 const Addr KSeg3Base = ULL(0xE0000000);
95 inline Addr Phys2K0Seg(Addr addr)
97 return addr | KSeg0Base;
101 const unsigned VABits = 32;
102 const unsigned PABits = 32; // Is this correct?
103 const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
104 const Addr VAddrUnImplMask = ~VAddrImplMask;
105 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
106 inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
107 inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
109 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
111 ////////////////////////////////////////////////////////////////////////
117 INTLEVEL_SOFTWARE_MIN = 4,
118 INTLEVEL_SOFTWARE_MAX = 19,
120 INTLEVEL_EXTERNAL_MIN = 20,
121 INTLEVEL_EXTERNAL_MAX = 34,
125 INTINDEX_ETHERNET = 0,
130 INTLEVEL_SERIAL = 33,
132 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
138 mode_kernel = 0, // kernel
139 mode_supervisor = 1, // supervisor
140 mode_user = 2, // user mode
141 mode_debug = 3, // debug mode
142 mode_number // number of modes
145 // return a no-op instruction... used for instruction fetch faults
146 const ExtMachInst NoopMachInst = 0x00000000;
148 const int LogVMPageSize = 13; // 8K bytes
149 const int VMPageSize = (1 << LogVMPageSize);
151 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
153 const int MachineBytes = 4;
154 const int WordBytes = 4;
155 const int HalfwordBytes = 2;
156 const int ByteBytes = 1;
158 const int ANNOTE_NONE = 0;
159 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
161 const bool HasUnalignedMemAcc = true;
163 } // namespace MipsISA
165 #endif // __ARCH_MIPS_ISA_TRAITS_HH__