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3 * Copyright (c) 2007 MIPS Technologies, Inc.
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34 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
35 #define __ARCH_MIPS_ISA_TRAITS_HH__
37 #include "arch/mips/types.hh"
38 #include "base/types.hh"
39 #include "config/full_system.hh"
40 #include "cpu/static_inst_fwd.hh"
42 namespace LittleEndianGuest {}
47 using namespace LittleEndianGuest;
49 StaticInstPtr decodeInst(ExtMachInst);
51 // MIPS DOES have a delay slot
52 #define ISA_HAS_DELAY_SLOT 1
54 const Addr PageShift = 13;
55 const Addr PageBytes = ULL(1) << PageShift;
56 const Addr Page_Mask = ~(PageBytes - 1);
57 const Addr PageOffset = PageBytes - 1;
60 ////////////////////////////////////////////////////////////////////////
65 const Addr PteShift = 3;
66 const Addr NPtePageShift = PageShift - PteShift;
67 const Addr NPtePage = ULL(1) << NPtePageShift;
68 const Addr PteMask = NPtePage - 1;
70 //// All 'Mapped' segments go through the TLB
71 //// All other segments are translated by dropping the MSB, to give
72 //// the corresponding physical address
73 // User Segment - Mapped
74 const Addr USegBase = ULL(0x0);
75 const Addr USegEnd = ULL(0x7FFFFFFF);
77 // Kernel Segment 0 - Unmapped
78 const Addr KSeg0End = ULL(0x9FFFFFFF);
79 const Addr KSeg0Base = ULL(0x80000000);
80 const Addr KSeg0Mask = ULL(0x1FFFFFFF);
82 // Kernel Segment 1 - Unmapped, Uncached
83 const Addr KSeg1End = ULL(0xBFFFFFFF);
84 const Addr KSeg1Base = ULL(0xA0000000);
85 const Addr KSeg1Mask = ULL(0x1FFFFFFF);
87 // Kernel/Supervisor Segment - Mapped
88 const Addr KSSegEnd = ULL(0xDFFFFFFF);
89 const Addr KSSegBase = ULL(0xC0000000);
91 // Kernel Segment 3 - Mapped
92 const Addr KSeg3End = ULL(0xFFFFFFFF);
93 const Addr KSeg3Base = ULL(0xE0000000);
96 inline Addr Phys2K0Seg(Addr addr)
98 return addr | KSeg0Base;
102 const unsigned VABits = 32;
103 const unsigned PABits = 32; // Is this correct?
104 const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
105 const Addr VAddrUnImplMask = ~VAddrImplMask;
106 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
107 inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
108 inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
110 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
112 ////////////////////////////////////////////////////////////////////////
118 INTLEVEL_SOFTWARE_MIN = 4,
119 INTLEVEL_SOFTWARE_MAX = 19,
121 INTLEVEL_EXTERNAL_MIN = 20,
122 INTLEVEL_EXTERNAL_MAX = 34,
126 INTINDEX_ETHERNET = 0,
131 INTLEVEL_SERIAL = 33,
133 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
139 mode_kernel = 0, // kernel
140 mode_supervisor = 1, // supervisor
141 mode_user = 2, // user mode
142 mode_debug = 3, // debug mode
143 mode_number // number of modes
146 // return a no-op instruction... used for instruction fetch faults
147 const ExtMachInst NoopMachInst = 0x00000000;
149 const int LogVMPageSize = 13; // 8K bytes
150 const int VMPageSize = (1 << LogVMPageSize);
152 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
154 const int MachineBytes = 4;
155 const int WordBytes = 4;
156 const int HalfwordBytes = 2;
157 const int ByteBytes = 1;
159 const int ANNOTE_NONE = 0;
160 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
162 const bool HasUnalignedMemAcc = true;
164 } // namespace MipsISA
166 #endif // __ARCH_MIPS_ISA_TRAITS_HH__