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34 * Authors: Gabe M. Black
39 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
40 #define __ARCH_MIPS_ISA_TRAITS_HH__
42 #include "arch/mips/types.hh"
43 #include "config/full_system.hh"
44 #include "sim/host.hh"
46 namespace LittleEndianGuest {};
54 using namespace LittleEndianGuest;
56 StaticInstPtr decodeInst(ExtMachInst);
58 // MIPS DOES have a delay slot
59 #define ISA_HAS_DELAY_SLOT 1
61 const Addr PageShift = 13;
62 const Addr PageBytes = ULL(1) << PageShift;
63 const Addr Page_Mask = ~(PageBytes - 1);
64 const Addr PageOffset = PageBytes - 1;
67 ////////////////////////////////////////////////////////////////////////
72 const Addr PteShift = 3;
73 const Addr NPtePageShift = PageShift - PteShift;
74 const Addr NPtePage = ULL(1) << NPtePageShift;
75 const Addr PteMask = NPtePage - 1;
77 //// All 'Mapped' segments go through the TLB
78 //// All other segments are translated by dropping the MSB, to give
79 //// the corresponding physical address
80 // User Segment - Mapped
81 const Addr USegBase = ULL(0x0);
82 const Addr USegEnd = ULL(0x7FFFFFFF);
84 // Kernel Segment 0 - Unmapped
85 const Addr KSeg0End = ULL(0x9FFFFFFF);
86 const Addr KSeg0Base = ULL(0x80000000);
87 const Addr KSeg0Mask = ULL(0x1FFFFFFF);
89 // Kernel Segment 1 - Unmapped, Uncached
90 const Addr KSeg1End = ULL(0xBFFFFFFF);
91 const Addr KSeg1Base = ULL(0xA0000000);
92 const Addr KSeg1Mask = ULL(0x1FFFFFFF);
94 // Kernel/Supervisor Segment - Mapped
95 const Addr KSSegEnd = ULL(0xDFFFFFFF);
96 const Addr KSSegBase = ULL(0xC0000000);
98 // Kernel Segment 3 - Mapped
99 const Addr KSeg3End = ULL(0xFFFFFFFF);
100 const Addr KSeg3Base = ULL(0xE0000000);
103 // For loading... XXX This maybe could be USegEnd?? --ali
104 const Addr LoadAddrMask = ULL(0xffffffffff);
106 inline Addr Phys2K0Seg(Addr addr)
108 // if (addr & PAddrUncachedBit43) {
109 // addr &= PAddrUncachedMask;
110 // addr |= PAddrUncachedBit40;
112 return addr | KSeg0Base;
115 ////////////////////////////////////////////////////////////////////////
121 INTLEVEL_SOFTWARE_MIN = 4,
122 INTLEVEL_SOFTWARE_MAX = 19,
124 INTLEVEL_EXTERNAL_MIN = 20,
125 INTLEVEL_EXTERNAL_MAX = 34,
129 INTINDEX_ETHERNET = 0,
134 INTLEVEL_SERIAL = 33,
136 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
143 mode_kernel = 0, // kernel
144 mode_supervisor = 1, // supervisor
145 mode_user = 2, // user mode
146 mode_debug = 3, // debug mode
147 mode_number // number of modes
150 inline mode_type getOperatingMode(MiscReg Stat)
152 if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
155 if((Stat & 0x18) == 0x8)
156 return mode_supervisor;
157 else if((Stat & 0x18) == 0x10)
159 else return mode_number;
164 // return a no-op instruction... used for instruction fetch faults
165 const ExtMachInst NoopMachInst = 0x00000000;
167 // Constants Related to the number of registers
168 const int NumIntArchRegs = 32;
169 const int NumIntSpecialRegs = 9;
170 const int NumFloatArchRegs = 32;
171 const int NumFloatSpecialRegs = 5;
173 const int NumShadowRegSets = 16; // Maximum number of shadow register sets
174 const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs
175 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
177 // Static instruction parameters
178 const int MaxInstSrcRegs = 10;
179 const int MaxInstDestRegs = 8;
181 // semantically meaningful register indices
182 const int ZeroReg = 0;
183 const int AssemblerReg = 1;
184 const int ReturnValueReg = 2;
185 const int ReturnValueReg1 = 2;
186 const int ReturnValueReg2 = 3;
187 const int ArgumentReg0 = 4;
188 const int ArgumentReg1 = 5;
189 const int ArgumentReg2 = 6;
190 const int ArgumentReg3 = 7;
191 const int KernelReg0 = 26;
192 const int KernelReg1 = 27;
193 const int GlobalPointerReg = 28;
194 const int StackPointerReg = 29;
195 const int FramePointerReg = 30;
196 const int ReturnAddressReg = 31;
198 const int ArgumentReg[] = {4, 5, 6, 7};
199 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
201 const int SyscallNumReg = ReturnValueReg1;
202 const int SyscallPseudoReturnReg = ReturnValueReg2;
203 const int SyscallSuccessReg = ArgumentReg3;
205 const int LogVMPageSize = 13; // 8K bytes
206 const int VMPageSize = (1 << LogVMPageSize);
208 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
210 const int MachineBytes = 4;
211 const int WordBytes = 4;
212 const int HalfwordBytes = 2;
213 const int ByteBytes = 1;
215 const int ANNOTE_NONE = 0;
216 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
218 // These help enumerate all the registers for dependence tracking.
219 const int FP_Base_DepTag = NumIntRegs;
220 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
222 // Enumerate names for 'Control' Registers in the CPU
223 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
224 // (Register Number-Register Select) Summary of Register
225 //------------------------------------------------------
226 // The first set of names classify the CP0 names as Register Banks
227 // for easy indexing when using the 'RD + SEL' index combination
228 // in CP0 instructions.
230 Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3
235 CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15
244 EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23
253 EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24
255 Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33
258 PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
259 PageGrain = Ctrl_Base_DepTag + 41,
261 Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55
268 HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63
270 BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71
272 Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79
274 EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87
276 Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95
278 Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103
283 Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111
285 EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119
287 PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127,
290 Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135
300 LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143
302 WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151
311 WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159
320 XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
326 Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191
332 DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199
334 PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207
343 ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215
345 CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223
350 TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231
359 TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239
369 ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247
371 DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256
373 LLFlag = Ctrl_Base_DepTag + 257,
378 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
380 const int NumMiscRegs = NumControlRegs;
382 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
387 using namespace MipsISA;
389 #endif // __ARCH_MIPS_ISA_TRAITS_HH__