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33 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
34 #define __ARCH_MIPS_ISA_TRAITS_HH__
36 #include "arch/mips/types.hh"
37 #include "arch/mips/mips_core_specific.hh"
38 #include "config/full_system.hh"
39 #include "sim/host.hh"
41 namespace LittleEndianGuest {};
49 using namespace LittleEndianGuest;
51 StaticInstPtr decodeInst(ExtMachInst);
53 // MIPS DOES have a delay slot
54 #define ISA_HAS_DELAY_SLOT 1
56 const Addr PageShift = 13;
57 const Addr PageBytes = ULL(1) << PageShift;
58 const Addr Page_Mask = ~(PageBytes - 1);
59 const Addr PageOffset = PageBytes - 1;
62 ////////////////////////////////////////////////////////////////////////
67 const Addr PteShift = 3;
68 const Addr NPtePageShift = PageShift - PteShift;
69 const Addr NPtePage = ULL(1) << NPtePageShift;
70 const Addr PteMask = NPtePage - 1;
72 //// All 'Mapped' segments go through the TLB
73 //// All other segments are translated by dropping the MSB, to give
74 //// the corresponding physical address
75 // User Segment - Mapped
76 const Addr USegBase = ULL(0x0);
77 const Addr USegEnd = ULL(0x7FFFFFFF);
79 // Kernel Segment 0 - Unmapped
80 const Addr KSeg0End = ULL(0x9FFFFFFF);
81 const Addr KSeg0Base = ULL(0x80000000);
82 const Addr KSeg0Mask = ULL(0x1FFFFFFF);
84 // Kernel Segment 1 - Unmapped, Uncached
85 const Addr KSeg1End = ULL(0xBFFFFFFF);
86 const Addr KSeg1Base = ULL(0xA0000000);
87 const Addr KSeg1Mask = ULL(0x1FFFFFFF);
89 // Kernel/Supervisor Segment - Mapped
90 const Addr KSSegEnd = ULL(0xDFFFFFFF);
91 const Addr KSSegBase = ULL(0xC0000000);
93 // Kernel Segment 3 - Mapped
94 const Addr KSeg3End = ULL(0xFFFFFFFF);
95 const Addr KSeg3Base = ULL(0xE0000000);
98 // For loading... XXX This maybe could be USegEnd?? --ali
99 const Addr LoadAddrMask = ULL(0xffffffffff);
101 inline Addr Phys2K0Seg(Addr addr)
103 // if (addr & PAddrUncachedBit43) {
104 // addr &= PAddrUncachedMask;
105 // addr |= PAddrUncachedBit40;
107 return addr | KSeg0Base;
111 const unsigned VABits = 32;
112 const unsigned PABits = 32; // Is this correct?
113 const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
114 const Addr VAddrUnImplMask = ~VAddrImplMask;
115 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
116 inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
117 inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
119 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
121 ////////////////////////////////////////////////////////////////////////
127 INTLEVEL_SOFTWARE_MIN = 4,
128 INTLEVEL_SOFTWARE_MAX = 19,
130 INTLEVEL_EXTERNAL_MIN = 20,
131 INTLEVEL_EXTERNAL_MAX = 34,
135 INTINDEX_ETHERNET = 0,
140 INTLEVEL_SERIAL = 33,
142 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
149 mode_kernel = 0, // kernel
150 mode_supervisor = 1, // supervisor
151 mode_user = 2, // user mode
152 mode_debug = 3, // debug mode
153 mode_number // number of modes
156 inline mode_type getOperatingMode(MiscReg Stat)
158 if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
161 if((Stat & 0x18) == 0x8)
162 return mode_supervisor;
163 else if((Stat & 0x18) == 0x10)
165 else return mode_number;
170 // return a no-op instruction... used for instruction fetch faults
171 const ExtMachInst NoopMachInst = 0x00000000;
173 // Constants Related to the number of registers
174 const int NumIntArchRegs = 32;
175 const int NumIntSpecialRegs = 9;
176 const int NumFloatArchRegs = 32;
177 const int NumFloatSpecialRegs = 5;
179 const int NumShadowRegSets = 16; // Maximum number of shadow register sets
180 const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs
181 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
183 // Static instruction parameters
184 const int MaxInstSrcRegs = 10;
185 const int MaxInstDestRegs = 8;
187 // semantically meaningful register indices
188 const int ZeroReg = 0;
189 const int AssemblerReg = 1;
190 const int ReturnValueReg = 2;
191 const int ReturnValueReg1 = 2;
192 const int ReturnValueReg2 = 3;
193 const int ArgumentReg0 = 4;
194 const int ArgumentReg1 = 5;
195 const int ArgumentReg2 = 6;
196 const int ArgumentReg3 = 7;
197 const int KernelReg0 = 26;
198 const int KernelReg1 = 27;
199 const int GlobalPointerReg = 28;
200 const int StackPointerReg = 29;
201 const int FramePointerReg = 30;
202 const int ReturnAddressReg = 31;
204 const int ArgumentReg[] = {4, 5, 6, 7};
205 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
207 const int SyscallNumReg = ReturnValueReg1;
208 const int SyscallPseudoReturnReg = ReturnValueReg2;
209 const int SyscallSuccessReg = ArgumentReg3;
211 const int LogVMPageSize = 13; // 8K bytes
212 const int VMPageSize = (1 << LogVMPageSize);
214 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
216 const int MachineBytes = 4;
217 const int WordBytes = 4;
218 const int HalfwordBytes = 2;
219 const int ByteBytes = 1;
221 const int ANNOTE_NONE = 0;
222 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
224 // These help enumerate all the registers for dependence tracking.
225 const int FP_Base_DepTag = NumIntRegs;
226 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
228 // Enumerate names for 'Control' Registers in the CPU
229 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
230 // (Register Number-Register Select) Summary of Register
231 //------------------------------------------------------
232 // The first set of names classify the CP0 names as Register Banks
233 // for easy indexing when using the 'RD + SEL' index combination
234 // in CP0 instructions.
236 Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3
241 CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15
250 EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23
259 EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24
261 Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33
264 PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
265 PageGrain = Ctrl_Base_DepTag + 41,
267 Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55
274 HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63
276 BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71
278 Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79
280 EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87
282 Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95
284 Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103
289 Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111
291 EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119
293 PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127,
296 Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135
306 LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143
308 WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151
317 WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159
326 XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
332 Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191
338 DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199
340 PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207
349 ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215
351 CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223
356 TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231
365 TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239
375 ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247
377 DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256
379 LLFlag = Ctrl_Base_DepTag + 257,
384 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
386 const int NumMiscRegs = NumControlRegs;
388 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
393 using namespace MipsISA;
395 #endif // __ARCH_MIPS_ISA_TRAITS_HH__