src/arch/mips/isa_traits.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Korey Sewell
  30  *          Jaidev Patwardhan
  31  */
  32
  33 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
  34 #define __ARCH_MIPS_ISA_TRAITS_HH__
  35
  36 #include "arch/mips/types.hh"
  37 #include "arch/mips/mips_core_specific.hh"
  38 #include "config/full_system.hh"
  39 #include "sim/host.hh"
  40
  41 namespace LittleEndianGuest {};
  42
  43 #define TARGET_MIPS
  44
  45 class StaticInstPtr;
  46
  47 namespace MipsISA
  48 {
  49     using namespace LittleEndianGuest;
  50
  51     StaticInstPtr decodeInst(ExtMachInst);
  52
  53     // MIPS DOES have a delay slot
  54     #define ISA_HAS_DELAY_SLOT 1
  55
  56     const Addr PageShift = 13;
  57     const Addr PageBytes = ULL(1) << PageShift;
  58     const Addr Page_Mask = ~(PageBytes - 1);
  59     const Addr PageOffset = PageBytes - 1;
  60
  61
  62     ////////////////////////////////////////////////////////////////////////
  63     //
  64     //  Translation stuff
  65     //
  66
  67     const Addr PteShift = 3;
  68     const Addr NPtePageShift = PageShift - PteShift;
  69     const Addr NPtePage = ULL(1) << NPtePageShift;
  70     const Addr PteMask = NPtePage - 1;
  71
  72     //// All 'Mapped' segments go through the TLB
  73     //// All other segments are translated by dropping the MSB, to give
  74     //// the corresponding physical address
  75     // User Segment - Mapped
  76     const Addr USegBase = ULL(0x0);
  77     const Addr USegEnd = ULL(0x7FFFFFFF);
  78
  79     // Kernel Segment 0 - Unmapped
  80     const Addr KSeg0End = ULL(0x9FFFFFFF);
  81     const Addr KSeg0Base =  ULL(0x80000000);
  82     const Addr KSeg0Mask = ULL(0x1FFFFFFF);
  83
  84     // Kernel Segment 1 - Unmapped, Uncached
  85     const Addr KSeg1End = ULL(0xBFFFFFFF);
  86     const Addr KSeg1Base = ULL(0xA0000000);
  87     const Addr KSeg1Mask = ULL(0x1FFFFFFF);
  88
  89     // Kernel/Supervisor Segment - Mapped
  90     const Addr KSSegEnd = ULL(0xDFFFFFFF);
  91     const Addr KSSegBase = ULL(0xC0000000);
  92
  93     // Kernel Segment 3 - Mapped
  94     const Addr KSeg3End = ULL(0xFFFFFFFF);
  95     const Addr KSeg3Base = ULL(0xE0000000);
  96
  97
  98     // For loading... XXX This maybe could be USegEnd?? --ali
  99     const Addr LoadAddrMask = ULL(0xffffffffff);
 100
 101     inline Addr Phys2K0Seg(Addr addr)
 102     {
 103    //  if (addr & PAddrUncachedBit43) {
 104 //         addr &= PAddrUncachedMask;
 105 //         addr |= PAddrUncachedBit40;
 106 //     }
 107         return addr | KSeg0Base;
 108     }
 109
 110
 111     const unsigned VABits = 32;
 112     const unsigned PABits = 32; // Is this correct?
 113     const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
 114     const Addr VAddrUnImplMask = ~VAddrImplMask;
 115     inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
 116     inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
 117     inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
 118
 119     const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
 120
 121     ////////////////////////////////////////////////////////////////////////
 122     //
 123     //  Interrupt levels
 124     //
 125     enum InterruptLevels
 126     {
 127         INTLEVEL_SOFTWARE_MIN = 4,
 128         INTLEVEL_SOFTWARE_MAX = 19,
 129
 130         INTLEVEL_EXTERNAL_MIN = 20,
 131         INTLEVEL_EXTERNAL_MAX = 34,
 132
 133         INTLEVEL_IRQ0 = 20,
 134         INTLEVEL_IRQ1 = 21,
 135         INTINDEX_ETHERNET = 0,
 136         INTINDEX_SCSI = 1,
 137         INTLEVEL_IRQ2 = 22,
 138         INTLEVEL_IRQ3 = 23,
 139
 140         INTLEVEL_SERIAL = 33,
 141
 142         NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
 143     };
 144
 145
 146     // MIPS modes
 147     enum mode_type
 148     {
 149         mode_kernel = 0,                // kernel
 150         mode_supervisor = 1,    // supervisor
 151         mode_user = 2,          // user mode
 152         mode_debug = 3,         // debug mode
 153         mode_number                     // number of modes
 154     };
 155
 156   inline mode_type getOperatingMode(MiscReg Stat)
 157   {
 158     if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
 159       return mode_kernel;
 160     else{
 161       if((Stat & 0x18) == 0x8)
 162         return mode_supervisor;
 163       else if((Stat & 0x18) == 0x10)
 164         return mode_user;
 165       else return mode_number;
 166     }
 167   }
 168
 169
 170     // return a no-op instruction... used for instruction fetch faults
 171     const ExtMachInst NoopMachInst = 0x00000000;
 172
 173     // Constants Related to the number of registers
 174     const int NumIntArchRegs = 32;
 175     const int NumIntSpecialRegs = 9;
 176     const int NumFloatArchRegs = 32;
 177     const int NumFloatSpecialRegs = 5;
 178
 179     const int NumShadowRegSets = 16; // Maximum number of shadow register sets
 180     const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs;        //HI & LO Regs
 181     const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
 182
 183     // Static instruction parameters
 184     const int MaxInstSrcRegs = 10;
 185     const int MaxInstDestRegs = 8;
 186
 187     // semantically meaningful register indices
 188     const int ZeroReg = 0;
 189     const int AssemblerReg = 1;
 190     const int ReturnValueReg = 2;
 191     const int ReturnValueReg1 = 2;
 192     const int ReturnValueReg2 = 3;
 193     const int ArgumentReg0 = 4;
 194     const int ArgumentReg1 = 5;
 195     const int ArgumentReg2 = 6;
 196     const int ArgumentReg3 = 7;
 197     const int KernelReg0 = 26;
 198     const int KernelReg1 = 27;
 199     const int GlobalPointerReg = 28;
 200     const int StackPointerReg = 29;
 201     const int FramePointerReg = 30;
 202     const int ReturnAddressReg = 31;
 203
 204     const int ArgumentReg[] = {4, 5, 6, 7};
 205     const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
 206
 207     const int SyscallNumReg = ReturnValueReg1;
 208     const int SyscallPseudoReturnReg = ReturnValueReg2;
 209     const int SyscallSuccessReg = ArgumentReg3;
 210
 211     const int LogVMPageSize = 13;       // 8K bytes
 212     const int VMPageSize = (1 << LogVMPageSize);
 213
 214     const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
 215
 216     const int MachineBytes = 4;
 217     const int WordBytes = 4;
 218     const int HalfwordBytes = 2;
 219     const int ByteBytes = 1;
 220
 221     const int ANNOTE_NONE = 0;
 222     const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 223
 224     // These help enumerate all the registers for dependence tracking.
 225     const int FP_Base_DepTag = NumIntRegs;
 226     const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
 227
 228     // Enumerate names for 'Control' Registers in the CPU
 229     // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
 230     // (Register Number-Register Select) Summary of Register
 231     //------------------------------------------------------
 232     // The first set of names classify the CP0 names as Register Banks
 233     // for easy indexing when using the 'RD + SEL' index combination
 234     // in CP0 instructions.
 235     enum MiscRegTags {
 236         Index = Ctrl_Base_DepTag + 0,       //Bank 0: 0 - 3
 237         MVPControl,
 238         MVPConf0,
 239         MVPConf1,
 240
 241         CP0_Random = Ctrl_Base_DepTag + 8,      //Bank 1: 8 - 15
 242         VPEControl,
 243         VPEConf0,
 244         VPEConf1,
 245         YQMask,
 246         VPESchedule,
 247         VPEScheFBack,
 248         VPEOpt,
 249
 250         EntryLo0 = Ctrl_Base_DepTag + 16,   //Bank 2: 16 - 23
 251         TCStatus,
 252         TCBind,
 253         TCRestart,
 254         TCHalt,
 255         TCContext,
 256         TCSchedule,
 257         TCScheFBack,
 258
 259         EntryLo1 = Ctrl_Base_DepTag + 24,   // Bank 3: 24
 260
 261         Context = Ctrl_Base_DepTag + 32,    // Bank 4: 32 - 33
 262         ContextConfig,
 263
 264         PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
 265         PageGrain = Ctrl_Base_DepTag + 41,
 266
 267         Wired = Ctrl_Base_DepTag + 48,          //Bank 6:48-55
 268         SRSConf0,
 269         SRSConf1,
 270         SRSConf2,
 271         SRSConf3,
 272         SRSConf4,
 273
 274         HWRena = Ctrl_Base_DepTag + 56,         //Bank 7: 56-63
 275
 276         BadVAddr = Ctrl_Base_DepTag + 64,       //Bank 8: 64-71
 277
 278         Count = Ctrl_Base_DepTag + 72,          //Bank 9: 72-79
 279
 280         EntryHi = Ctrl_Base_DepTag + 80,        //Bank 10: 80-87
 281
 282         Compare = Ctrl_Base_DepTag + 88,        //Bank 11: 88-95
 283
 284         Status = Ctrl_Base_DepTag + 96,         //Bank 12: 96-103
 285         IntCtl,
 286         SRSCtl,
 287         SRSMap,
 288
 289         Cause = Ctrl_Base_DepTag + 104,         //Bank 13: 104-111
 290
 291         EPC = Ctrl_Base_DepTag + 112,           //Bank 14: 112-119
 292
 293         PRId = Ctrl_Base_DepTag + 120,          //Bank 15: 120-127,
 294         EBase,
 295
 296         Config = Ctrl_Base_DepTag + 128,        //Bank 16: 128-135
 297         Config1,
 298         Config2,
 299         Config3,
 300         Config4,
 301         Config5,
 302         Config6,
 303         Config7,
 304
 305
 306         LLAddr = Ctrl_Base_DepTag + 136,        //Bank 17: 136-143
 307
 308         WatchLo0 = Ctrl_Base_DepTag + 144,      //Bank 18: 144-151
 309         WatchLo1,
 310         WatchLo2,
 311         WatchLo3,
 312         WatchLo4,
 313         WatchLo5,
 314         WatchLo6,
 315         WatchLo7,
 316
 317         WatchHi0 = Ctrl_Base_DepTag + 152,     //Bank 19: 152-159
 318         WatchHi1,
 319         WatchHi2,
 320         WatchHi3,
 321         WatchHi4,
 322         WatchHi5,
 323         WatchHi6,
 324         WatchHi7,
 325
 326         XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
 327
 328                            //Bank 21: 168-175
 329
 330                            //Bank 22: 176-183
 331
 332         Debug = Ctrl_Base_DepTag + 184,       //Bank 23: 184-191
 333         TraceControl1,
 334         TraceControl2,
 335         UserTraceData,
 336         TraceBPC,
 337
 338         DEPC = Ctrl_Base_DepTag + 192,        //Bank 24: 192-199
 339
 340         PerfCnt0 = Ctrl_Base_DepTag + 200,    //Bank 25: 200-207
 341         PerfCnt1,
 342         PerfCnt2,
 343         PerfCnt3,
 344         PerfCnt4,
 345         PerfCnt5,
 346         PerfCnt6,
 347         PerfCnt7,
 348
 349         ErrCtl = Ctrl_Base_DepTag + 208,      //Bank 26: 208-215
 350
 351         CacheErr0 = Ctrl_Base_DepTag + 216,   //Bank 27: 216-223
 352         CacheErr1,
 353         CacheErr2,
 354         CacheErr3,
 355
 356         TagLo0 = Ctrl_Base_DepTag + 224,      //Bank 28: 224-231
 357         DataLo1,
 358         TagLo2,
 359         DataLo3,
 360         TagLo4,
 361         DataLo5,
 362         TagLo6,
 363         DataLo7,
 364
 365         TagHi0 = Ctrl_Base_DepTag + 232,      //Bank 29: 232-239
 366         DataHi1,
 367         TagHi2,
 368         DataHi3,
 369         TagHi4,
 370         DataHi5,
 371         TagHi6,
 372         DataHi7,
 373
 374
 375         ErrorEPC = Ctrl_Base_DepTag + 240,    //Bank 30: 240-247
 376
 377         DESAVE = Ctrl_Base_DepTag + 248,       //Bank 31: 248-256
 378
 379         LLFlag = Ctrl_Base_DepTag + 257,
 380
 381         NumControlRegs
 382     };
 383
 384     const int TotalDataRegs = NumIntRegs + NumFloatRegs;
 385
 386     const int NumMiscRegs = NumControlRegs;
 387
 388     const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 389
 390
 391 };
 392
 393 using namespace MipsISA;
 394
 395 #endif // __ARCH_MIPS_ISA_TRAITS_HH__