src/arch/mips/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Korey Sewell
  30  */
  31
  32 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
  33 #define __ARCH_MIPS_ISA_TRAITS_HH__
  34
  35 #include "arch/mips/max_inst_regs.hh"
  36 #include "arch/mips/types.hh"
  37 #include "sim/host.hh"
  38
  39 namespace LittleEndianGuest {};
  40
  41 #define TARGET_MIPS
  42
  43 class StaticInstPtr;
  44
  45 namespace MipsISA
  46 {
  47     using namespace LittleEndianGuest;
  48     using MipsISAInst::MaxInstSrcRegs;
  49     using MipsISAInst::MaxInstDestRegs;
  50
  51     StaticInstPtr decodeInst(ExtMachInst);
  52
  53     // MIPS DOES a delay slot
  54     #define ISA_HAS_DELAY_SLOT 1
  55
  56     const Addr PageShift = 13;
  57     const Addr PageBytes = ULL(1) << PageShift;
  58     const Addr PageMask = ~(PageBytes - 1);
  59     const Addr PageOffset = PageBytes - 1;
  60
  61     // return a no-op instruction... used for instruction fetch faults
  62     const ExtMachInst NoopMachInst = 0x00000000;
  63
  64     // Constants Related to the number of registers
  65     const int NumIntArchRegs = 32;
  66     const int NumIntSpecialRegs = 9;
  67     const int NumFloatArchRegs = 32;
  68     const int NumFloatSpecialRegs = 5;
  69
  70     // semantically meaningful register indices
  71     const int ZeroReg = 0;
  72     const int AssemblerReg = 1;
  73     const int ReturnValueReg = 2;
  74     const int ReturnValueReg1 = 2;
  75     const int ReturnValueReg2 = 3;
  76
  77     const int ArgumentReg[] = {4, 5, 6, 7};
  78     const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
  79
  80     const int KernelReg0 = 26;
  81     const int KernelReg1 = 27;
  82     const int GlobalPointerReg = 28;
  83     const int StackPointerReg = 29;
  84     const int FramePointerReg = 30;
  85     const int ReturnAddressReg = 31;
  86
  87     const int SyscallNumReg = ReturnValueReg1;
  88     const int SyscallPseudoReturnReg = ReturnValueReg2;
  89     const int SyscallSuccessReg = ArgumentReg[3];
  90
  91     const int LogVMPageSize = 13;       // 8K bytes
  92     const int VMPageSize = (1 << LogVMPageSize);
  93
  94     const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
  95
  96     const int MachineBytes = 4;
  97     const int WordBytes = 4;
  98     const int HalfwordBytes = 2;
  99     const int ByteBytes = 1;
 100
 101     const int ANNOTE_NONE = 0;
 102     const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 103
 104     // Enumerate names for 'Control' Registers in the CPU
 105     // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
 106     // (Register Number-Register Select) Summary of Register
 107     //------------------------------------------------------
 108     // The first set of names classify the CP0 names as Register Banks
 109     // for easy indexing when using the 'RD + SEL' index combination
 110     // in CP0 instructions.
 111     enum MiscRegTags {
 112         Index = 0,       //Bank 0: 0 - 3
 113         MVPControl,
 114         MVPConf0,
 115         MVPConf1,
 116
 117         Random = 8,      //Bank 1: 8 - 15
 118         VPEControl,
 119         VPEConf0,
 120         VPEConf1,
 121         YQMask,
 122         VPESchedule,
 123         VPEScheFBack,
 124         VPEOpt,
 125
 126         EntryLo0 = 16,   //Bank 2: 16 - 23
 127         TCStatus,
 128         TCBind,
 129         TCRestart,
 130         TCHalt,
 131         TCContext,
 132         TCSchedule,
 133         TCScheFBack,
 134
 135         EntryLo1 = 24,   // Bank 3: 24
 136
 137         Context = 32,    // Bank 4: 32 - 33
 138         ContextConfig,
 139
 140         //PageMask = 40, //Bank 5: 40 - 41
 141         PageGrain = 41,
 142
 143         Wired = 48,          //Bank 6:48-55
 144         SRSConf0,
 145         SRSConf1,
 146         SRSConf2,
 147         SRSConf3,
 148         SRSConf4,
 149
 150         HWRena = 56,         //Bank 7: 56-63
 151
 152         BadVAddr = 64,       //Bank 8: 64-71
 153
 154         Count = 72,          //Bank 9: 72-79
 155
 156         EntryHi = 80,        //Bank 10: 80-87
 157
 158         Compare = 88,        //Bank 11: 88-95
 159
 160         Status = 96,         //Bank 12: 96-103
 161         IntCtl,
 162         SRSCtl,
 163         SRSMap,
 164
 165         Cause = 104,         //Bank 13: 104-111
 166
 167         EPC = 112,           //Bank 14: 112-119
 168
 169         PRId = 120,          //Bank 15: 120-127,
 170         EBase,
 171
 172         Config = 128,        //Bank 16: 128-135
 173         Config1,
 174         Config2,
 175         Config3,
 176         Config4,
 177         Config5,
 178         Config6,
 179         Config7,
 180
 181
 182         LLAddr = 136,        //Bank 17: 136-143
 183
 184         WatchLo0 = 144,      //Bank 18: 144-151
 185         WatchLo1,
 186         WatchLo2,
 187         WatchLo3,
 188         WatchLo4,
 189         WatchLo5,
 190         WatchLo6,
 191         WatchLo7,
 192
 193         WatchHi0 = 152,     //Bank 19: 152-159
 194         WatchHi1,
 195         WatchHi2,
 196         WatchHi3,
 197         WatchHi4,
 198         WatchHi5,
 199         WatchHi6,
 200         WatchHi7,
 201
 202         XCContext64 = 160, //Bank 20: 160-167
 203
 204                            //Bank 21: 168-175
 205
 206                            //Bank 22: 176-183
 207
 208         Debug = 184,       //Bank 23: 184-191
 209         TraceControl1,
 210         TraceControl2,
 211         UserTraceData,
 212         TraceBPC,
 213
 214         DEPC = 192,        //Bank 24: 192-199
 215
 216         PerfCnt0 = 200,    //Bank 25: 200-207
 217         PerfCnt1,
 218         PerfCnt2,
 219         PerfCnt3,
 220         PerfCnt4,
 221         PerfCnt5,
 222         PerfCnt6,
 223         PerfCnt7,
 224
 225         ErrCtl = 208,      //Bank 26: 208-215
 226
 227         CacheErr0 = 216,   //Bank 27: 216-223
 228         CacheErr1,
 229         CacheErr2,
 230         CacheErr3,
 231
 232         TagLo0 = 224,      //Bank 28: 224-231
 233         DataLo1,
 234         TagLo2,
 235         DataLo3,
 236         TagLo4,
 237         DataLo5,
 238         TagLo6,
 239         DataLo7,
 240
 241         TagHi0 = 232,      //Bank 29: 232-239
 242         DataHi1,
 243         TagHi2,
 244         DataHi3,
 245         TagHi4,
 246         DataHi5,
 247         TagHi6,
 248         DataHi7,
 249
 250
 251         ErrorEPC = 240,    //Bank 30: 240-247
 252
 253         DESAVE = 248,       //Bank 31: 248-256
 254
 255         LLFlag = 257,
 256
 257         NumControlRegs
 258     };
 259
 260     const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
 261     const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
 262     const int NumMiscRegs = NumControlRegs;
 263
 264     const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 265
 266     const int TotalDataRegs = NumIntRegs + NumFloatRegs;
 267
 268     // These help enumerate all the registers for dependence tracking.
 269     const int FP_Base_DepTag = NumIntRegs;
 270     const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
 271 };
 272
 273 using namespace MipsISA;
 274
 275 #endif // __ARCH_MIPS_ISA_TRAITS_HH__