2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
33 #define __ARCH_MIPS_ISA_TRAITS_HH__
35 #include "arch/mips/max_inst_regs.hh"
36 #include "arch/mips/types.hh"
37 #include "sim/host.hh"
39 namespace LittleEndianGuest {};
47 using namespace LittleEndianGuest;
48 using MipsISAInst::MaxInstSrcRegs;
49 using MipsISAInst::MaxInstDestRegs;
51 StaticInstPtr decodeInst(ExtMachInst);
53 // MIPS DOES a delay slot
54 #define ISA_HAS_DELAY_SLOT 1
56 const Addr PageShift = 13;
57 const Addr PageBytes = ULL(1) << PageShift;
58 const Addr PageMask = ~(PageBytes - 1);
59 const Addr PageOffset = PageBytes - 1;
61 // return a no-op instruction... used for instruction fetch faults
62 const ExtMachInst NoopMachInst = 0x00000000;
64 // Constants Related to the number of registers
65 const int NumIntArchRegs = 32;
66 const int NumIntSpecialRegs = 9;
67 const int NumFloatArchRegs = 32;
68 const int NumFloatSpecialRegs = 5;
70 // semantically meaningful register indices
71 const int ZeroReg = 0;
72 const int AssemblerReg = 1;
73 const int ReturnValueReg = 2;
74 const int ReturnValueReg1 = 2;
75 const int ReturnValueReg2 = 3;
77 const int ArgumentReg[] = {4, 5, 6, 7};
78 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
80 const int KernelReg0 = 26;
81 const int KernelReg1 = 27;
82 const int GlobalPointerReg = 28;
83 const int StackPointerReg = 29;
84 const int FramePointerReg = 30;
85 const int ReturnAddressReg = 31;
87 const int SyscallNumReg = ReturnValueReg1;
88 const int SyscallPseudoReturnReg = ReturnValueReg2;
89 const int SyscallSuccessReg = ArgumentReg[3];
91 const int LogVMPageSize = 13; // 8K bytes
92 const int VMPageSize = (1 << LogVMPageSize);
94 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
96 const int MachineBytes = 4;
97 const int WordBytes = 4;
98 const int HalfwordBytes = 2;
99 const int ByteBytes = 1;
101 const int ANNOTE_NONE = 0;
102 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
104 // Enumerate names for 'Control' Registers in the CPU
105 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
106 // (Register Number-Register Select) Summary of Register
107 //------------------------------------------------------
108 // The first set of names classify the CP0 names as Register Banks
109 // for easy indexing when using the 'RD + SEL' index combination
110 // in CP0 instructions.
112 Index = 0, //Bank 0: 0 - 3
117 Random = 8, //Bank 1: 8 - 15
126 EntryLo0 = 16, //Bank 2: 16 - 23
135 EntryLo1 = 24, // Bank 3: 24
137 Context = 32, // Bank 4: 32 - 33
140 //PageMask = 40, //Bank 5: 40 - 41
143 Wired = 48, //Bank 6:48-55
150 HWRena = 56, //Bank 7: 56-63
152 BadVAddr = 64, //Bank 8: 64-71
154 Count = 72, //Bank 9: 72-79
156 EntryHi = 80, //Bank 10: 80-87
158 Compare = 88, //Bank 11: 88-95
160 Status = 96, //Bank 12: 96-103
165 Cause = 104, //Bank 13: 104-111
167 EPC = 112, //Bank 14: 112-119
169 PRId = 120, //Bank 15: 120-127,
172 Config = 128, //Bank 16: 128-135
182 LLAddr = 136, //Bank 17: 136-143
184 WatchLo0 = 144, //Bank 18: 144-151
193 WatchHi0 = 152, //Bank 19: 152-159
202 XCContext64 = 160, //Bank 20: 160-167
208 Debug = 184, //Bank 23: 184-191
214 DEPC = 192, //Bank 24: 192-199
216 PerfCnt0 = 200, //Bank 25: 200-207
225 ErrCtl = 208, //Bank 26: 208-215
227 CacheErr0 = 216, //Bank 27: 216-223
232 TagLo0 = 224, //Bank 28: 224-231
241 TagHi0 = 232, //Bank 29: 232-239
251 ErrorEPC = 240, //Bank 30: 240-247
253 DESAVE = 248, //Bank 31: 248-256
260 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
261 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
262 const int NumMiscRegs = NumControlRegs;
264 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
266 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
268 // These help enumerate all the registers for dependence tracking.
269 const int FP_Base_DepTag = NumIntRegs;
270 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
273 using namespace MipsISA;
275 #endif // __ARCH_MIPS_ISA_TRAITS_HH__