src/arch/mips/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Gabe Black
  30  *          Korey Sewell
  31  *          Jaidev Patwardhan
  32  */
  33
  34 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
  35 #define __ARCH_MIPS_ISA_TRAITS_HH__
  36
  37 #include "arch/mips/mips_core_specific.hh"
  38 #include "arch/mips/types.hh"
  39 #include "base/types.hh"
  40 #include "config/full_system.hh"
  41 #include "cpu/static_inst_fwd.hh"
  42
  43 namespace LittleEndianGuest {}
  44
  45 namespace MipsISA
  46 {
  47
  48 using namespace LittleEndianGuest;
  49
  50 StaticInstPtr decodeInst(ExtMachInst);
  51
  52 // MIPS DOES have a delay slot
  53 #define ISA_HAS_DELAY_SLOT 1
  54
  55 const Addr PageShift = 13;
  56 const Addr PageBytes = ULL(1) << PageShift;
  57 const Addr Page_Mask = ~(PageBytes - 1);
  58 const Addr PageOffset = PageBytes - 1;
  59
  60
  61 ////////////////////////////////////////////////////////////////////////
  62 //
  63 //  Translation stuff
  64 //
  65
  66 const Addr PteShift = 3;
  67 const Addr NPtePageShift = PageShift - PteShift;
  68 const Addr NPtePage = ULL(1) << NPtePageShift;
  69 const Addr PteMask = NPtePage - 1;
  70
  71 //// All 'Mapped' segments go through the TLB
  72 //// All other segments are translated by dropping the MSB, to give
  73 //// the corresponding physical address
  74 // User Segment - Mapped
  75 const Addr USegBase = ULL(0x0);
  76 const Addr USegEnd = ULL(0x7FFFFFFF);
  77
  78 // Kernel Segment 0 - Unmapped
  79 const Addr KSeg0End = ULL(0x9FFFFFFF);
  80 const Addr KSeg0Base =  ULL(0x80000000);
  81 const Addr KSeg0Mask = ULL(0x1FFFFFFF);
  82
  83 // Kernel Segment 1 - Unmapped, Uncached
  84 const Addr KSeg1End = ULL(0xBFFFFFFF);
  85 const Addr KSeg1Base = ULL(0xA0000000);
  86 const Addr KSeg1Mask = ULL(0x1FFFFFFF);
  87
  88 // Kernel/Supervisor Segment - Mapped
  89 const Addr KSSegEnd = ULL(0xDFFFFFFF);
  90 const Addr KSSegBase = ULL(0xC0000000);
  91
  92 // Kernel Segment 3 - Mapped
  93 const Addr KSeg3End = ULL(0xFFFFFFFF);
  94 const Addr KSeg3Base = ULL(0xE0000000);
  95
  96
  97 inline Addr Phys2K0Seg(Addr addr)
  98 {
  99     return addr | KSeg0Base;
 100 }
 101
 102
 103 const unsigned VABits = 32;
 104 const unsigned PABits = 32; // Is this correct?
 105 const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
 106 const Addr VAddrUnImplMask = ~VAddrImplMask;
 107 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
 108 inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
 109 inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
 110
 111 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
 112
 113 ////////////////////////////////////////////////////////////////////////
 114 //
 115 //  Interrupt levels
 116 //
 117 enum InterruptLevels
 118 {
 119     INTLEVEL_SOFTWARE_MIN = 4,
 120     INTLEVEL_SOFTWARE_MAX = 19,
 121
 122     INTLEVEL_EXTERNAL_MIN = 20,
 123     INTLEVEL_EXTERNAL_MAX = 34,
 124
 125     INTLEVEL_IRQ0 = 20,
 126     INTLEVEL_IRQ1 = 21,
 127     INTINDEX_ETHERNET = 0,
 128     INTINDEX_SCSI = 1,
 129     INTLEVEL_IRQ2 = 22,
 130     INTLEVEL_IRQ3 = 23,
 131
 132     INTLEVEL_SERIAL = 33,
 133
 134     NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
 135 };
 136
 137 // MIPS modes
 138 enum mode_type
 139 {
 140     mode_kernel = 0,        // kernel
 141     mode_supervisor = 1,    // supervisor
 142     mode_user = 2,          // user mode
 143     mode_debug = 3,         // debug mode
 144     mode_number             // number of modes
 145 };
 146
 147 // return a no-op instruction... used for instruction fetch faults
 148 const ExtMachInst NoopMachInst = 0x00000000;
 149
 150 const int LogVMPageSize = 13;       // 8K bytes
 151 const int VMPageSize = (1 << LogVMPageSize);
 152
 153 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
 154
 155 const int MachineBytes = 4;
 156 const int WordBytes = 4;
 157 const int HalfwordBytes = 2;
 158 const int ByteBytes = 1;
 159
 160 const int ANNOTE_NONE = 0;
 161 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 162
 163 const bool HasUnalignedMemAcc = true;
 164
 165 } // namespace MipsISA
 166
 167 #endif // __ARCH_MIPS_ISA_TRAITS_HH__