2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
33 #define __ARCH_MIPS_ISA_TRAITS_HH__
35 #include "arch/mips/types.hh"
36 #include "sim/host.hh"
38 namespace LittleEndianGuest {};
46 using namespace LittleEndianGuest;
48 StaticInstPtr decodeInst(ExtMachInst);
50 // MIPS DOES a delay slot
51 #define ISA_HAS_DELAY_SLOT 1
53 const Addr PageShift = 13;
54 const Addr PageBytes = ULL(1) << PageShift;
55 const Addr PageMask = ~(PageBytes - 1);
56 const Addr PageOffset = PageBytes - 1;
58 // return a no-op instruction... used for instruction fetch faults
59 const ExtMachInst NoopMachInst = 0x00000000;
61 // Constants Related to the number of registers
62 const int NumIntArchRegs = 32;
63 const int NumIntSpecialRegs = 9;
64 const int NumFloatArchRegs = 32;
65 const int NumFloatSpecialRegs = 5;
67 // Static instruction parameters
68 const int MaxInstSrcRegs = 5;
69 const int MaxInstDestRegs = 4;
71 // semantically meaningful register indices
72 const int ZeroReg = 0;
73 const int AssemblerReg = 1;
74 const int ReturnValueReg = 2;
75 const int ReturnValueReg1 = 2;
76 const int ReturnValueReg2 = 3;
78 const int ArgumentReg[] = {4, 5, 6, 7};
79 const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
81 const int KernelReg0 = 26;
82 const int KernelReg1 = 27;
83 const int GlobalPointerReg = 28;
84 const int StackPointerReg = 29;
85 const int FramePointerReg = 30;
86 const int ReturnAddressReg = 31;
88 const int SyscallNumReg = ReturnValueReg1;
89 const int SyscallPseudoReturnReg = ReturnValueReg2;
90 const int SyscallSuccessReg = ArgumentReg[3];
92 const int LogVMPageSize = 13; // 8K bytes
93 const int VMPageSize = (1 << LogVMPageSize);
95 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
97 const int MachineBytes = 4;
98 const int WordBytes = 4;
99 const int HalfwordBytes = 2;
100 const int ByteBytes = 1;
102 const int ANNOTE_NONE = 0;
103 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
105 // Enumerate names for 'Control' Registers in the CPU
106 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
107 // (Register Number-Register Select) Summary of Register
108 //------------------------------------------------------
109 // The first set of names classify the CP0 names as Register Banks
110 // for easy indexing when using the 'RD + SEL' index combination
111 // in CP0 instructions.
113 Index = 0, //Bank 0: 0 - 3
118 Random = 8, //Bank 1: 8 - 15
127 EntryLo0 = 16, //Bank 2: 16 - 23
136 EntryLo1 = 24, // Bank 3: 24
138 Context = 32, // Bank 4: 32 - 33
141 //PageMask = 40, //Bank 5: 40 - 41
144 Wired = 48, //Bank 6:48-55
151 HWRena = 56, //Bank 7: 56-63
153 BadVAddr = 64, //Bank 8: 64-71
155 Count = 72, //Bank 9: 72-79
157 EntryHi = 80, //Bank 10: 80-87
159 Compare = 88, //Bank 11: 88-95
161 Status = 96, //Bank 12: 96-103
166 Cause = 104, //Bank 13: 104-111
168 EPC = 112, //Bank 14: 112-119
170 PRId = 120, //Bank 15: 120-127,
173 Config = 128, //Bank 16: 128-135
183 LLAddr = 136, //Bank 17: 136-143
185 WatchLo0 = 144, //Bank 18: 144-151
194 WatchHi0 = 152, //Bank 19: 152-159
203 XCContext64 = 160, //Bank 20: 160-167
209 Debug = 184, //Bank 23: 184-191
215 DEPC = 192, //Bank 24: 192-199
217 PerfCnt0 = 200, //Bank 25: 200-207
226 ErrCtl = 208, //Bank 26: 208-215
228 CacheErr0 = 216, //Bank 27: 216-223
233 TagLo0 = 224, //Bank 28: 224-231
242 TagHi0 = 232, //Bank 29: 232-239
252 ErrorEPC = 240, //Bank 30: 240-247
254 DESAVE = 248, //Bank 31: 248-256
261 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
262 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
263 const int NumMiscRegs = NumControlRegs;
265 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
267 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
269 // These help enumerate all the registers for dependence tracking.
270 const int FP_Base_DepTag = NumIntRegs;
271 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
274 using namespace MipsISA;
276 #endif // __ARCH_MIPS_ISA_TRAITS_HH__