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28 * Authors: Steve Reinhardt
31 #ifndef __ARCH_MIPS_LOCKED_MEM_HH__
32 #define __ARCH_MIPS_LOCKED_MEM_HH__
37 * ISA-specific helper functions for locked memory accesses.
40 #include "arch/isa_traits.hh"
41 #include "base/misc.hh"
42 #include "base/trace.hh"
43 #include "mem/request.hh"
50 handleLockedRead(XC *xc, Request *req)
52 xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf);
53 xc->setMiscRegNoEffect(LLFlag, true);
54 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
55 req->threadId(), req->getPaddr() & ~0xf);
61 handleLockedWrite(XC *xc, Request *req)
63 if (req->isUncacheable()) {
64 // Funky Turbolaser mailbox access...don't update
65 // result register (see stq_c in decoder.isa)
68 // standard store conditional
69 bool lock_flag = xc->readMiscRegNoEffect(LLFlag);
70 Addr lock_addr = xc->readMiscRegNoEffect(LLAddr);
72 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
73 // Lock flag not set or addr mismatch in CPU;
74 // don't even bother sending to memory system
76 xc->setMiscRegNoEffect(LLFlag, false);
78 // the rest of this code is not architectural;
79 // it's just a debugging aid to help detect
80 // livelock by warning on long sequences of failed
82 int stCondFailures = xc->readStCondFailures();
84 xc->setStCondFailures(stCondFailures);
85 if (stCondFailures % 10 == 0) {
86 warn("%i: context %d: %d consecutive "
87 "store conditional failures\n",
88 curTick, xc->contextId(), stCondFailures);
91 if (stCondFailures == 5000) {
92 panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n");
96 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n",
98 } else if ((req->getPaddr() & ~0xf) != lock_addr) {
99 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n",
102 // store conditional failed already, so don't issue it to mem
111 } // namespace MipsISA